參數(shù)資料
型號： FDC37B787-NS
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 外設(shè)及接口
英文描述： Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
中文描述： MULTIFUNCTION PERIPHERAL, PQFP128
封裝： ROHS COMPLIANT, QFP-128
文件頁數(shù)： 39/249頁
文件大小： 932K
代理商： FDC37B787-NS
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very responsive to the service request. This is the
desired case for use with a "fast" system.
A high value of threshold (i.e. 12) is used with a
"sluggish" system by affording a long latency
period after a service request, but results in more
frequent service requests.
Non-DMA Mode - Transfers from the FIFO to the
Host
The FINT pin and RQM bits in the Main Status
Register are activated when the FIFO contains
(16-<threshold>) bytes or the last bytes of a full
sector have been placed in the FIFO. The FINT
pin can be used for interrupt-driven systems, and
RQM can be used for polled systems. The host
must respond to the request by reading data from
the FIFO. This process is repeated until the last
byte is transferred out of the FIFO. The FDC will
deactivate the FINT pin and RQM bit when the
FIFO becomes empty.
Non-DMA Mode - Transfers from the Host to the
FIFO
The FINT pin and RQM bit in the Main Status
Register are activated upon entering the execution
phase of data transfer commands. The host must
respond to the request by writing data into the
FIFO. The FINT pin and RQM bit remain true until
the FIFO becomes full. They are set true again
when the FIFO has <threshold> bytes remaining in
the FIFO. The FINT pin will also be deactivated if
TC and nDACK both go inactive. The FDC enters
the result phase after the last byte is taken by the
FDC from the FIFO (i.e. FIFO empty condition).
DMA Mode - Transfers from the FIFO to the Host
The FDC activates the DDRQ pin when the FIFO
contains (16 - <threshold>) bytes, or the last byte
of a full sector transfer has been placed in the
FIFO. The DMA controller must respond to the
request by reading data from the FIFO. The FDC
will deactivate the DDRQ pin when the FIFO
becomes empty. FDRQ goes inactive after
nDACK goes active for the last byte of a data
transfer (or on the active edge of nIOR, on the last
byte, if no edge is present on nDACK). A data
39
underrun may occur if FDRQ is not removed in
time to prevent an unwanted cycle.
DMA Mode - Transfers from the Host to the FIFO.
The FDC activates the FDRQ pin when entering
the execution phase of the data transfer
commands. The DMA controller must respond by
activating the nDACK and nIOW pins and placing
data in the FIFO. FDRQ remains active until the
FIFO becomes full. FDRQ is again set true when
the FIFO has <threshold> bytes remaining in the
FIFO. The FDC will also deactivate the FDRQ pin
when TC becomes true (qualified by nDACK),
indicating that no more data is required. FDRQ
goes inactive after nDACK goes active for the last
byte of a data transfer (or on the active edge of
nIOW of the last byte, if no edge is present on
nDACK). A data overrun may occur if FDRQ is
not removed in time to prevent an unwanted cycle.
Data Transfer Termination
The FDC supports terminal count explicitly through
the
TC
pin
and
implicitly
underrun/overrun
and
functions. For full sector transfers, the EOT
parameter can define the last sector to be
transferred in a single or multi-sector transfer.
If the last sector to be transferred is a partial
sector, the host can stop transferring the data in
mid-sector, and the FDC will continue to complete
the sector as if a hardware TC was
received. The only difference between these
implicit functions and TC is that they return
"abnormal termination" result status. Such status
indications can be ignored if they were expected.
Note that when the host is sending data to the
FIFO of the FDC, the internal sector count will be
complete when the FDC reads the last byte from
its side of the FIFO. There may be a delay in the
removal of the transfer request signal of up to the
time taken for the FDC to read the last 16 bytes
from the FIFO. The host must tolerate this delay.
Result Phase
through
the
end-of-track
(EOT)
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