參數(shù)資料
型號： FDC37B787-NS
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 外設(shè)及接口
英文描述： Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
中文描述： MULTIFUNCTION PERIPHERAL, PQFP128
封裝： ROHS COMPLIANT, QFP-128
文件頁數(shù)： 38/249頁
文件大?。?/td> 932K
代理商： FDC37B787-NS
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Model 30 mode
- (IDENT low, MFM low)
This mode supports PS/2 Model 30 configuration
and register set. The DMA enable bit of the DOR
becomes valid (FINTR and DRQ can be hi Z), TC
is active high and DENSEL is active low.
DMA TRANSFERS
DMA transfers are enabled with the Specify
command and are initiated by the FDC by
activating the FDRQ pin during a data transfer
command. The FIFO is enabled directly by
asserting nDACK and addresses need not be
valid.
Note that if the DMA controller (i.e. 8237A) is
programmed to function in verify mode, a pseudo
read is performed by the FDC based only on
nDACK. This mode is only available when the
FDC has been configured into byte mode (FIFO
disabled) and is programmed to do a read. With
the FIFO enabled, the FDC can perform the above
operation by using the new Verify command; no
DMA operation is needed.
Two DMA transfer modes are supported for the
FDC: Single Transfer and Burst Transfer. In the
case of the single transfer, the DMA Req goes
active at the start of the DMA cycle, and the DMA
Req is deasserted after the nDACK. In the case of
the burst transfer, the Req
is held active until the
last transfer (independent of nDACK). See timing
diagrams for more information.
Burst mode is enabled via Bit[1] of CRF0 in
Logical Device 0. Setting Bit[1]=0 enables burst
mode; the default is Bit[1]=1, for non-burst mode.
CONTROLLER PHASES
For simplicity, command handling in the FDC can
be divided into three phases: Command,
Execution, and Result. Each phase is described in
the following sections.
Command Phase
After a reset, the FDC enters the command phase
and is ready to accept a command from the host.
For each of the commands, a defined set of
38
command code bytes and parameter bytes has to
be written to the FDC before the command phase
is complete. (Please refer to TABLE 20 for the
command set descriptions). These bytes of data
must be transferred in the order prescribed.
Before writing to the FDC, the host must examine
the RQM and DIO bits of the Main Status Register.
RQM and DIO must be equal to "1" and "0"
respectively before command bytes may be
written. RQM is set false by the FDC after each
write cycle until the received byte is processed.
The FDC asserts RQM again to request each
parameter byte of the command unless an illegal
command condition is detected. After the last
parameter byte is received, RQM remains "0" and
the FDC automatically enters the next phase as
defined by the command definition.
The FIFO is disabled during the command phase
to provide for the proper handling of the "Invalid
Command" condition.
Execution Phase
All data transfers to or from the FDC occur during
the execution phase, which can proceed in DMA
or non-DMA mode as indicated in the Specify
command.
After a reset, the FIFO is disabled. Each data byte
is transferred by an FINT or FDRQ depending on
the DMA mode. The Configure command can
enable the FIFO and set the FIFO threshold value.
The following paragraphs detail the operation of
the FIFO flow control. In these descriptions,
<threshold> is defined as the number of bytes
available to the FDC when service is requested
from the host and ranges from 1 to 16. The
parameter FIFOTHR, which the user programs, is
one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases. The host reads (writes)
from (to) the FIFO until empty (full), then the
transfer request goes inactive. The host must be
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