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| 型號： | EVAL-ADUC7128QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 64/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV FOR ADUC7128 |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters |
| 設(shè)計資源： | ADUC7128 Dev System Schematic ADUC7128 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7128 |
| 所含物品： | 評估板、電源、纜線、軟件、仿真器和說明文檔 |
| 產(chǎn)品目錄頁面： | 739 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADUC7128BSTZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP |
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Rev. 0 | Page 67 of 92
I2CxSRX Register
Name
Address
Default Value
Access
I2C0SRX
0xFFFF0808
0x00
R
I2C1SRX
0xFFFF0908
0x00
R
I2CxSRX is a receive register for the slave channel.
I2CxSTX Register
Name
Address
Default Value
Access
I2C0STX
0xFFFF080C
0x00
W
I2C1STX
0xFFFF090C
0x00
W
I2CxSTX is a transmit register for the slave channel.
I2CxMRX Register
Name
Address
Default Value
Access
I2C0MRX
0xFFFF0810
0x00
R
I2C1MRX
0xFFFF0910
0x00
R
I2CxMRX is a receive register for the master channel.
I2CxMTX Register
Name
Address
Default Value
Access
I2C0MTX
0xFFFF0814
0x00
W
I2C1MTX
0xFFFF0914
0x00
W
I2CxMTX is a transmit register for the master channel.
I2CxCNT Register
Name
Address
Default Value
Access
I2C0CNT
0xFFFF0818
0x00
R/W
I2C1CNT
0xFFFF0918
0x00
R/W
I2CxCNT is a master receive data count register. If a master read
transfer sequence is initiated, the I2CxCNT register denotes the
number of bytes (1) to be read from the slave device. By default
this counter is 0, which corresponds to the expected one byte.
I2CxADR Register
Name
Address
Default Value
Access
I2C0ADR
0xFFFF081C
0x00
R/W
I2C1ADR
0xFFFF091C
0x00
R/W
I2CxADR is a master address byte register. The I2CxADR value
is the device address that the master wants to communicate
with. It is automatically transmitted at the start of a master
transfer sequence if there is no valid data in the I2CxMTX
register when the master enable bit is set.
I2CxBYT Register
Name
Address
Default Value
Access
I2C0BYT
0xFFFF0824
0x00
R/W
I2C1BYT
0xFFFF0924
0x00
R/W
I2CxBYT is a broadcast byte register.
I2CxALT Register
Name
Address
Default Value
Access
I2C0ALT
0xFFFF0828
0x00
R/W
I2C1ALT
0xFFFF0928
0x00
R/W
I2CxALT is a hardware general call ID register used in slave mode.
I2CxCFG Register
Name
Address
Default Value
Access
I2C0CFG
0xFFFF082C
0x00
R/W
I2C1CFG
0xFFFF092C
0x00
R/W
I2CxCFG is a configuration register.
Table 94. I2C0CFG MMR Bit Designations
Bit
Description
31:15
Reserved. These bits should be written by the user as 0.
14
Enable Stop Interrupt.
Set by user to generate an interrupt upon receiving a stop condition and after receiving a valid start condition and matching
address.
Cleared by user to disable the generation of an interrupt upon receiving a stop condition.
13
Reserved. This bit should be written by the user as 0.
12
Reserved. This bit should be written by the user as 0.
11
Enable Stretch SCL. Holds SCL low.
Set by user to stretch the SCL line.
Cleared by user to disable stretching of the SCL line.
10
Reserved. This bit should be written by the user as 0.
9
Slave Tx FIFO Request Interrupt Enable.
Cleared by user to generate an interrupt request just after the negative edge of the clock for the R/W bit. This allows the user to
input data into the slave Tx FIFO if it is empty. At 400 kSPS, and with the core clock running at 41.78 MHz, the user has 45 clock
cycles to take appropriate action, taking interrupt latency into account.
Set by user to disable the slave Tx FIFO request interrupt.
8
General Call Status Bit Clear.
Set by user to clear the general call status bits.
Cleared automatically by hardware after the general call status bits have been cleared.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADUC7128QSPZ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC |
| EVAL-ADUC7129QSPZ | 制造商:Analog Devices 功能描述:- Bulk |
| EVAL-ADUC812QS | 制造商:Analog Devices 功能描述:DEVELOPMENT KIT SYSTEM |
| EVAL-ADUC812QSP | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter㈢, Multichannel 12-Bit ADC with Embedded Flash MCU |
| EVAL-ADUC812QSZ | 功能描述:BOARD EVALUATION FOR ADUC812 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
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