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| 型號： | EVAL-ADUC7128QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/92頁 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR ADUC7128 |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters |
| 設(shè)計(jì)資源： | ADUC7128 Dev System Schematic ADUC7128 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7128 |
| 所含物品： | 評估板、電源、纜線、軟件、仿真器和說明文檔 |
| 產(chǎn)品目錄頁面： | 739 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADUC7128BSTZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP |
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ADuC7128/ADuC7129
Rev. 0 | Page 36 of 92
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture is described for the three different modes of
operation: differential mode, pseudo differential mode, and
single-ended mode.
Differential Mode
The ADuC7128/ADuC7129 contain a successive approximation
show simplified schematics of the ADC in acquisition and
conversion phase, respectively. The ADC comprises control logic,
a SAR, and two capacitive DACs. In Figure 37 (the acquisition
phase), SW3 is closed and SW1 and SW2 are in Position A. The
comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
AIN0
AIN13
MUX
CHANNEL+
CHANNEL–
06020-
033
Figure 37. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 38), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic generates
the ADC output code. The output impedances of the sources
driving the VIN+ pin and the VIN pin must be matched; otherwise,
the two inputs have different settling times, resulting in errors.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
AIN0
AIN13
MUX
CHANNEL+
CHANNEL–
0602
0-
03
4
Figure 38. ADC Conversion Phase
Pseudo Differential Mode
In pseudo differential mode, Channel is linked to the VIN pin
of the ADuC7128/ADuC7129, and SW2 switches between A
(Channel) and B (VREF). The VIN pin must be connected to
ground or a low voltage. The input signal on VIN+ can then vary
from VIN to VREF + VIN. Note that VIN must be chosen so that
VREF + VIN does not exceed AVDD.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
AIN0
AIN13
VIN–
MUX
CHANNEL+
CHANNEL–
0602
0-
03
5
Figure 39. ADC in Pseudo Differential Mode
Single-Ended Mode
In single-ended mode, SW2 is always connected internally to
ground. The VIN pin can be floating. The input signal range on
VIN+ is 0 V to VREF.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
CS
AIN0
AIN13
MUX
CHANNEL+
CHANNEL–
0602
0-
03
6
Figure 40. ADC in Single-Ended Mode
Analog Input Structure
Figure 41 shows the equivalent circuit of the analog input
structure of the ADC. The four diodes provide ESD protection
for the analog inputs. Care must be taken to ensure that the
analog input signals never exceed the supply rails by more than
300 mV. Voltage in excess of 300 mV would cause these diodes to
become forward biased and start conducting into the substrate.
These diodes can conduct up to 10 mA without causing
irreversible damage to the part.
The C1 capacitors in Figure 41 are typically 4 pF and can be
primarily attributed to pin capacitance. The resistors are lumped
components made up of the on resistance of the switches. The
value of these resistors is typically about 100 Ω. The C2 capacitors
are the ADC sampling capacitors and have a capacitance of 16 pF
typical.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADUC7128QSPZ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC |
| EVAL-ADUC7129QSPZ | 制造商:Analog Devices 功能描述:- Bulk |
| EVAL-ADUC812QS | 制造商:Analog Devices 功能描述:DEVELOPMENT KIT SYSTEM |
| EVAL-ADUC812QSP | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter㈢, Multichannel 12-Bit ADC with Embedded Flash MCU |
| EVAL-ADUC812QSZ | 功能描述:BOARD EVALUATION FOR ADUC812 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
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