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| 型號： | EVAL-ADUC7128QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV FOR ADUC7128 |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters |
| 設(shè)計資源： | ADUC7128 Dev System Schematic ADUC7128 Gerber Files |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7128 |
| 所含物品： | 評估板、電源、纜線、軟件、仿真器和說明文檔 |
| 產(chǎn)品目錄頁面： | 739 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADUC7128BSTZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP |
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ADuC7128/ADuC7129
Rev. 0 | Page 49 of 92
OSCILLATOR AND PLL—POWER CONTROL
The ADuC7128/ADuC7129 integrate a 32.768 kHz oscillator,
a clock divider, and a PLL. The PLL locks onto a multiple (1275)
of the internal oscillator to provide a stable 41.78 MHz clock for
the system. The core can operate at this frequency, or at binary
submultiples of it, to allow power saving. The default core clock
is the PLL clock divided by 8 (CD = 3) or 5.2 MHz. The core
clock frequency can be output on the ECLK pin as described in
Figure 48. Note that when the ECLK pin is used to output the
core clock, the output signal is not buffered and is not suitable
for use as a clock source to an external device without an
external buffer.
A power-down mode is available on the ADuC7128/ADuC7129.
The operating mode, clocking mode, and programmable clock
divider are controlled via two MMRs, PLLCON (see Table 61) and
POWCON (see Table 62). PLLCON controls operating mode of
the clock system, and POWCON controls the core clock
frequency and the power-down mode.
132.768kHz ±3%
AT POWER UP
40.78MHz
OCLK 32.768kHz
WATCHDOG
TIMER
INT. 32kHz1
OSCILLATOR
CRYSTAL
OSCILLATOR
WAKEUP
TIMER
MDCLK
HCLK
PLL
CORE
I2C
UCLK
ANALOG
PERIPHERALS
/2CD
CD
XCLKO
XCLKI
P0.7/XCLK
P0.7/ECLK
06020-
043
Figure 48. Clocking System
External Crystal Selection
To switch to an external crystal, use the following procedure:
1.
Enable the Timer2 interrupt and configure it for a timeout
period of >120 μs.
2.
Follow the write sequence to the PLLCON register, setting
the MDCLK bits to 01 and clearing the OSEL bit.
3.
Force the part into nap mode by following the correct write
sequence to the POWCON register.
4.
When the part is interrupted from nap mode by the Timer2
interrupt source, the clock source has switched to the
external clock.
Example Source Code
T2LD = 5;
TCON = 0x480;
while ((T2VAL == t2val_old) || (T2VAL >
3)) //ensures timer value loaded
IRQEN = 0x10;
//enable T2 interrupt
PLLKEY1 = 0xAA;
PLLCON = 0x01;
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON = 0x27;
// Set Core into Nap mode
POWKEY2 = 0xF4;
In noisy environments, noise can couple to the external crystal
pins, and PLL may lose lock momentarily. A PLL interrupt is
provided in the interrupt controller. The core clock is immediately
halted, and this interrupt is serviced only when the lock is restored.
In case of crystal loss, the watchdog timer should be used. During
initialization, a test on the RSTSTA can determine if the reset
came from the watchdog timer.
External Clock Selection
To switch to an external clock on P0.7, configure P0.7 in
Mode 1. The external clock can be up to 44 MHz, providing
the tolerance is 1%.
Example Source Code
T2LD = 5;
TCON = 0x480;
while ((T2VAL == t2val_old) || (T2VAL >
3)) //ensures timer value loaded
IRQEN = 0x10;
//enable T2 interrupt
PLLKEY1 = 0xAA;
PLLCON = 0x03; //Select external clock
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON = 0x27; // Set Core into Nap mode
POWKEY2 = 0xF4;
Power Control System
A choice of operating modes is available on the ADuC7128/
ADuC7129. Table 58 describes what part of the ADuC7128/
ADuC7129 is powered on in the different modes and indicates
the power-up time. Table 59 gives some typical values of the total
current consumption (analog + digital supply currents) in the
different modes, depending on the clock divider bits. The ADC is
turned off.
Note that these values also include current consumption of the
regulator and other parts on the test board on which these values
were measured.
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| EVAL-ADUC812QSZ | 功能描述:BOARD EVALUATION FOR ADUC812 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 標準包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
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