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參數(shù)資料
| 型號： | EVAL-ADUC7128QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 51/92頁 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR ADUC7128 |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters |
| 設(shè)計資源： | ADUC7128 Dev System Schematic ADUC7128 Gerber Files |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7128 |
| 所含物品： | 評估板、電源、纜線、軟件、仿真器和說明文檔 |
| 產(chǎn)品目錄頁面： | 739 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADUC7128BSTZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP |
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ADuC7128/ADuC7129
Rev. 0 | Page 55 of 92
QENCLR Register
Name
Address
Default Value
Access
QENCLR
0xFFFF0F14
0x00000000
R/W
Writing any value to the QENCLR register clears the QENVAL
register to 0x0000. The bits in this register are undefined.
QENSET Register
Name
Address
Default Value
Access
QENSET
0xFFFF0F18
0x00000000
R/W
Writing any value to the QENSET register loads the QENVAL
register with the value in QENDAT. The bits in this register are
undefined.
Note that the interrupt conditions are OR’ed together to form
one interrupt to the interrupt controller. The interrupt service
routine should check the QENSTA register to find out the cause
of the interrupt.
The S1 and S2 inputs appear as the QENS1 and QENS2
inputs in the GPIO list.
The motor speed can be measured by using the capture
facility in Timer0 or Timer1.
An overflow of either timer can be checked by using an ISR
or by checking IRQSIG.
The counter with the quadrature encoder is gray encoded to
ensure reliable data transfer across clock boundaries. When an
underflow or overflow occur, the count value does not jump to
the other end of the scale; instead, the direction of count changes.
When this happens, the value in QENDAT is subtracted from the
value derived from the gray count.
When the value in QENDAT changes, the value read back from
QENVAL changes. However, the gray encoded value does not
change. This only occurs after an underflow or overflow. If the
value in QENDAT changes, there must be a write to QENSET
or QENCLR to ensure a valid number is read back from QENVAL.
GENERAL-PURPOSE I/O
The ADuC7128/ADuC7129 provide 40 general-purpose,
bidirectional I/O (GPIO) pins. All I/O pins are 5 V tolerant,
meaning that the GPIOs support an input voltage of 5 V. In
general, many of the GPIO pins have multiple functions (see
Table 70). By default, the GPIO pins are configured in GPIO mode.
All GPIO pins have an internal pull-up resistor (of about 100 kΩ)
and their drive capability is 1.6 mA. Note that a maximum of
20 GPIO can drive 1.6 mA at the same time. The following GPIOs
have programmable pull-up: P0.0, P0.4, P0.5, P0.6, P0.7, and
the eight GPIOs of P1.
The 40 GPIOs are grouped in five ports: Port 0 to Port 4. Each
port is controlled by four or five MMRs, with x representing the
port number.
GPxCON Register
Name
Address
Default Value
Access
GP0CON
0xFFFF0D00
0x00000000
R/W
GP1CON
0xFFFF0D04
0x00000000
R/W
GP2CON
0xFFFF0D08
0x00000000
R/W
GP3CON
0xFFFF0D0C
0x11111111
R/W
GP4CON
0xFFFF0D10
0x00000000
R/W
Note that the kernel changes P0.6 from its default configuration
at reset (MRST) to GPIO mode. If MRST is used for external
circuitry, an external pull-up resistor should be used to ensure
that the level on P0.6 does not drop when the kernel switches
mode. Otherwise, P0.6 goes low for the reset period. For example,
if MRST is required for power-down, it can be reconfigured in
GP0CON MMR.
The input level of any GPIO can be read at any time in the
GPxDAT MMR, even when the pin is configured in a mode
other than GPIO. The PLA input is always active.
When the ADuC7128/ADuC7129 enter a power-saving mode,
the GPIO pins retain their state.
GPxCON is the Port x control register, and it selects the
function of each pin of Port x, as described in Table 70.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADUC7128QSPZ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC |
| EVAL-ADUC7129QSPZ | 制造商:Analog Devices 功能描述:- Bulk |
| EVAL-ADUC812QS | 制造商:Analog Devices 功能描述:DEVELOPMENT KIT SYSTEM |
| EVAL-ADUC812QSP | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter㈢, Multichannel 12-Bit ADC with Embedded Flash MCU |
| EVAL-ADUC812QSZ | 功能描述:BOARD EVALUATION FOR ADUC812 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 標準包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
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