ADC Clock Speed (fADC = F<" />
參數(shù)資料
型號(hào): EVAL-ADUC7128QSPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 28/92頁(yè)
文件大?。?/td> 0K
描述: KIT DEV FOR ADUC7128
產(chǎn)品培訓(xùn)模塊: ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
設(shè)計(jì)資源: ADUC7128 Dev System Schematic
ADUC7128 Gerber Files
標(biāo)準(zhǔn)包裝: 1
系列: QuickStart™ PLUS 套件
類型: MCU
適用于相關(guān)產(chǎn)品: ADuC7128
所含物品: 評(píng)估板、電源、纜線、軟件、仿真器和說(shuō)明文檔
產(chǎn)品目錄頁(yè)面: 739 (CN2011-ZH PDF)
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ADuC7128/ADuC7129
Rev. 0 | Page 34 of 92
Table 33. ADCCON MMR Bit Designations
Bit
Value
Description
12:10
ADC Clock Speed (fADC = FCORE, Conversion = 19 ADC Clocks + Acquisition Time).
000
fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz.
001
fADC/2 (default value).
010
fADC/4.
011
fADC/8.
100
fADC/16.
101
fADC/32.
9:8
ADC Acquisition Time (Number of ADC Clocks).
00
2 clocks.
01
4 clocks.
10
8 clocks (default value).
11
16 clocks.
7
Enable Conversion.
Set by user to enable conversion mode.
Cleared by user to disable conversion mode.
6
Reserved. This bit should be set to 0 by the user.
5
ADC Power Control.
Set by user to place the ADC in normal mode. The ADC must be powered up for at least 5 μs before it converts correctly.
Cleared by user to place the ADC in power-down mode.
Conversion Mode.
00
Single-ended Mode.
01
Differential Mode.
10
Pseudo Differential Mode.
4:3
11
Reserved.
Conversion Type.
000
Enable CONVST pin as a conversion input.
001
Enable Timer1 as a conversion input.
010
Enable Timer0 as a conversion input.
011
Single Software Conversion. Set to 000 after conversion. Bit 7 of ADCCON MMR should be cleared after starting a single
software conversion to avoid further conversions triggered by the CONVST pin.
100
Continuous Software Conversion.
101
PLA Conversion.
110
PWM Conversion.
2:0
Other
Reserved.
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