參數(shù)資料
型號(hào): EVAL-ADUC7128QSPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 40/92頁(yè)
文件大小: 0K
描述: KIT DEV FOR ADUC7128
產(chǎn)品培訓(xùn)模塊: ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
設(shè)計(jì)資源: ADUC7128 Dev System Schematic
ADUC7128 Gerber Files
標(biāo)準(zhǔn)包裝: 1
系列: QuickStart™ PLUS 套件
類(lèi)型: MCU
適用于相關(guān)產(chǎn)品: ADuC7128
所含物品: 評(píng)估板、電源、纜線、軟件、仿真器和說(shuō)明文檔
產(chǎn)品目錄頁(yè)面: 739 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: ADUC7128BSTZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP
ADUC7128BCPZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP
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ADuC7128/ADuC7129
Rev. 0 | Page 45 of 92
OTHER ANALOG PERIPHERALS
DAC
The ADuC7128/ADuC7129 feature a 10-bit current DAC that
can be used to generate user-defined waveforms or sine waves
generated by the DDS. The DAC consists of a 10-bit IDAC
followed by a current-to-voltage conversion.
The current output of the IDAC is passed through a resistor and
capacitor network where it is both filtered and converted to a
voltage. This voltage is then buffered by an op amp and passed
to the line driver.
For the DAC to function, the internal 2.5 V voltage reference
must be enabled and driven out onto an external capacitor,
REFCON = 0x01.
Once the DAC is enabled, users see a 5 mV drop in the internal
reference value. This is due to bias currents drawn from the
reference used in the DAC circuitry. It is recommended that if
using the DAC, it be left powered on to avoid seeing variations
in ADC results.
Table 49. DACCON MMR Bit Designations
Bit
Value
Description
10:9
Reserved. These bits should be written to 0 by the user.
8
Reserved. This bit should be written to 0 by the user.
7
Reserved. This bit should be written to 0 by the user.
6
Reserved. This bit should be written to 0 by the user.
5
Output Enable. This bit operates in all modes. In Line Driver mode, this bit should be set.
Set by user to enable the line driver output.
Cleared by user to disable the line driver output. In this mode the line driver output is high impedance.
4
Single-Ended or Differential Output Control.
Set by user to operate in differential mode, the output is the differential voltage between LD1TX and LD2TX. The voltage
output range is VREF/2 ± VREF/2.
Cleared by user to reference the LD1TX output to AGND. The voltage output range is AVDD/2 ± VREF/2.
3
Reserved. This bit should be set to 0 by the user.
Operation Mode Control. This bit selects the mode of operation of the DAC.
00
Power-Down.
01
Reserved.
10
Reserved.
2:1
11
DDS and DAC Mode. Selected by DACEN.
0
DAC Update Rate Control. This bit has no effect when in DDS mode.
Set by user to update the DAC on the negative edge of Timer1. This allows the user to use any one of the core CLK, OSC
CLK, baud CLK, or user CLK and divide these down by 1, 16, 256, or 32,768. A user can do waveform generation by
writing to the DAC data register from RAM and updating the DAC at regular intervals via Timer1.
Cleared by user to update the DAC on the negative edge of HCLK.
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