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| 型號： | EVAL-ADAU1761Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADAU1761 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻編解碼器 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1761 |
| 主要屬性： | 立體聲，24 位，8 ~ 96 kHz 采樣率，GUI 工具 |
| 次要屬性： | I²C 和 GPIO 接口，2 差分和 1 個立體聲單端模擬輸入和輸出 |
| 已供物品： | 2 個板，線纜，CD |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADAU1761BCPZ-RL-ND - IC SIGMADSP CODEC PLL 32LFCSP ADAU1761BCPZ-R7-ND - IC SIGMADSP CODEC PLL 32LFCSP ADAU1761BCPZ-ND - IC SIGMADSP CODEC PLL 32LFCSP |
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ADAU1761
Rev. C | Page 16 of 92
Pin No.
Mnemonic
Type1
Description
19
RHP
A_OUT
Right Headphone Output. Biased at AVDD/2.
20
LHP
A_OUT
Left Headphone Output. Biased at AVDD/2.
21
MONOOUT
A_OUT
Mono Output or Virtual Ground for Capless Headphone. Biased at AVDD/2 when set as mono
output.
22
AGND
PWR
Analog Ground. The AGND and DGND pins can be tied together on a common ground plane.
AGND should be decoupled locally to AVDD with a 100 nF capacitor.
23
AVDD
PWR
1.8 V to 3.3 V Analog Supply for ADC, Output Driver, and Input to Digital Supply Regulator.
This pin should be decoupled locally to AGND with a 100 nF capacitor.
24
DVDDOUT
PWR
Digital Core Supply Decoupling Point. The digital supply is generated from an on-board
regulator and does not require an external supply. DVDDOUT should be decoupled to DGND
with a 100 nF capacitor and a 10 μF capacitor.
25
DGND
PWR
Digital Ground. The AGND and DGND pins can be tied together on a common ground plane.
DGND should be decoupled to DVDDOUT and to IOVDD with 100 nF capacitors and 10 μF
capacitors.
26
ADC_SDATA/GPIO1
D_IO
ADC Serial Output Data (ADC_SDATA).
General-Purpose Input/Output 1 (GPIO1).
27
DAC_SDATA/GPIO0
D_IO
DAC Serial Input Data (DAC_SDATA).
General-Purpose Input/Output 0 (GPIO0).
28
BCLK/GPIO2
D_IO
Serial Data Port Bit Clock (BCLK).
General-Purpose Input/Output 2 (GPIO2).
29
LRCLK/GPIO3
D_IO
Serial Data Port Frame Clock (LRCLK).
General-Purpose Input/Output 3 (GPIO3).
30
ADDR1/CDATA
D_IN
I2C Address Bit 1 (ADDR1).
SPI Data Input (CDATA).
31
SDA/COUT
D_IO
I2C Data (SDA). This pin is a bidirectional open-collector input/output. The line connected to
this pin should have a 2 kΩ pull-up resistor.
SPI Data Output (COUT). This pin is used for reading back registers and memory locations. It is
three-state when an SPI read is not active.
32
SCL/CCLK
D_IN
I2C Clock (SCL). This pin is always an open-collector input when in I2C control mode. The line
connected to this pin should have a 2 kΩ pull-up resistor.
SPI Clock (CCLK). This pin can run continuously or be gated off between SPI transactions.
EP
Exposed Pad
Exposed Pad. The exposed pad is connected internally to the ADAU1761 grounds. For
increased reliability of the solder joints and maximum thermal capability, it is recommended
that the pad be soldered to the ground plane. See the Exposed Pad PCB Design section for
more information.
1 A_IN = analog input, A_OUT = analog output, D_IN = digital input, D_IO = digital input/output, PWR = power.
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| EVAL-ADAU1781Z | 功能描述:BOARD EVAL FOR ADAU1781 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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