I2C Read and Write Operations Figure 51 shows th" />
參數(shù)資料
型號(hào): EVAL-ADAU1761Z
廠商: Analog Devices Inc
文件頁數(shù): 35/92頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADAU1761
標(biāo)準(zhǔn)包裝: 1
系列: SigmaDSP®
主要目的: 音頻編解碼器
嵌入式: 是,DSP
已用 IC / 零件: ADAU1761
主要屬性: 立體聲,24 位,8 ~ 96 kHz 采樣率,GUI 工具
次要屬性: I²C 和 GPIO 接口,2 差分和 1 個(gè)立體聲單端模擬輸入和輸出
已供物品: 2 個(gè)板,線纜,CD
產(chǎn)品目錄頁面: 776 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: ADAU1761BCPZ-RL-ND - IC SIGMADSP CODEC PLL 32LFCSP
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ADAU1761BCPZ-ND - IC SIGMADSP CODEC PLL 32LFCSP
ADAU1761
Rev. C | Page 40 of 92
I2C Read and Write Operations
Figure 51 shows the format of a single-word write operation.
Every ninth clock pulse, the ADAU1761 issues an acknowledge
by pulling SDA low.
Figure 52 shows the format of a burst mode write sequence. This
figure shows an example of a write to sequential single-byte
registers. The ADAU1761 increments its subaddress register
after every byte because the requested subaddress corresponds
to a register or memory area with a 1-byte word length.
Figure 53 shows the format of a single-word read operation. Note
that the first R/W bit is 0, indicating a write operation. This is
because the subaddress still needs to be written to set up the
internal address. After the ADAU1761 acknowledges the receipt
of the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/W bit set to 1 (read).
This causes the ADAU1761 SDA to reverse and begin driving
data back to the master. The master then responds every ninth
pulse with an acknowledge pulse to the ADAU1761.
Figure 54 shows the format of a burst mode read sequence. This
figure shows an example of a read from sequential single-byte
registers. The ADAU1761 increments its subaddress register
after every byte because the requested subaddress corresponds
to a register or memory area with a 1-byte word length. The
ADAU1761 always decodes the subaddress and sets the auto-
increment circuit so that the address increments after the
appropriate number of bytes.
Figure 51 to Figure 54 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
S
Chip address,
R/W = 0
AS
Subaddress high byte
AS
Subaddress low byte
AS
Data Byte 1
P
Figure 51. Single-Word I2C Write Format
S
Chip address,
R/W = 0
AS
Subaddress
high byte
AS
Subaddress
low byte
AS
Data
Byte 1
AS
Data
Byte 2
AS
Data
Byte 3
AS
Data
Byte 4
AS
P
Figure 52. Burst Mode I2C Write Format
S
Chip address,
R/W = 0
AS
Subaddress high
byte
AS
Subaddress low
byte
AS
S
Chip address,
R/W = 1
AS
Data
Byte 1
P
Figure 53. Single-Word I2C Read Format
S
Chip address,
R/W = 0
AS
Subaddress
high byte
AS
Subaddress
low byte
AS
S
Chip address,
R/W = 1
AS
Data
Byte 1
AM
Data
Byte 2
AM
P
Figure 54. Burst Mode I2C Read Format
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