- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16848 > EVAL-ADAU1761Z (Analog Devices Inc)BOARD EVAL FOR ADAU1761 PDF資料下載
參數(shù)資料
| 型號： | EVAL-ADAU1761Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 43/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADAU1761 |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻編解碼器 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1761 |
| 主要屬性： | 立體聲，24 位，8 ~ 96 kHz 采樣率，GUI 工具 |
| 次要屬性： | I²C 和 GPIO 接口，2 差分和 1 個立體聲單端模擬輸入和輸出 |
| 已供物品： | 2 個板，線纜，CD |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADAU1761BCPZ-RL-ND - IC SIGMADSP CODEC PLL 32LFCSP ADAU1761BCPZ-R7-ND - IC SIGMADSP CODEC PLL 32LFCSP ADAU1761BCPZ-ND - IC SIGMADSP CODEC PLL 32LFCSP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當前第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
ADAU1761
Rev. C | Page 48 of 92
Table 27. Parameter RAM Read/Write Format (Single Address)
Byte 0
Byte 1
Byte 2
Byte 3
Bytes[4:6]
chip_adr[6:0], R/W
param_adr[15:8]
param_adr[7:0]
0000, param[27:24]
param[23:0]
Table 28. Parameter RAM Block Read/Write Format (Burst Mode)
Byte 0
Byte 1
Byte 2
Byte 3
Bytes[4:6]
Bytes[7:10]
Bytes[11:14]
chip_adr[6:0], R/W
param_adr[15:8]
param_adr[7:0]
0000, param[27:24]
param[23:0]
<—param_adr—>
param_adr + 1
param_adr + 2
Table 29. Program RAM Read/Write Format (Single Address)
Byte 0
Byte 1
Byte 2
Bytes[3:7]
chip_adr[6:0], R/W
prog_adr[15:8]
prog_adr[7:0]
prog[39:0]
Table 30. Program RAM Block Read/Write Format (Burst Mode)
Byte 0
Byte 1
Byte 2
Bytes[3:7]
Bytes[8:12]
Bytes[13:17]
chip_adr[6:0], R/W
prog_adr[15:8]
prog_adr[7:0]
prog[39:0]
<—prog_adr—>
prog_adr + 1
prog_adr + 2
SOFTWARE SAFELOAD
To update parameters in real time while avoiding pop and click
noises on the output, the ADAU1761 uses a software safeload
mechanism. The software safeload mechanism enables the
SigmaDSP core to load new parameters into RAM while guar-
anteeing that the parameters are not in use. This prevents an
undesirable condition where an instruction could execute with
a mix of old and new parameters.
SigmaStudio sets up the necessary code and parameters auto-
matically for new projects. The safeload code, along with other
initialization code, fills the first 39 locations in program RAM.
The first eight parameter RAM locations (Address 0x0000 to
Address 0x0007) are configured by default in SigmaStudio as
described in Table 31.
Table 31. Software Safeload Parameter RAM Defaults
Address (Hex)
Function
0x0000
Modulo RAM size
0x0001
Safeload Data 1
0x0002
Safeload Data 2
0x0003
Safeload Data 3
0x0004
Safeload Data 4
0x0005
Safeload Data 5
0x0006
Safeload target address (offset of 1)
0x0007
Number of words to write/safeload trigger
Address 0x0000, which controls the modulo RAM size, is set
by SigmaStudio and is based on the dynamic address generator
mode of the project.
Parameter RAM Address 0x0001 to Address 0x0005 are the five
data slots for storing the data to be safeloaded. The safeload
parameter space contains five data slots by default because most
standard signal processing algorithms have five parameters or less.
Address 0x0006 is the target address in parameter RAM (with
an offset of 1). This designates the first address to be written.
If more than one word is written, the address increments auto-
matically for each data-word. Up to five sequential parameter
RAM locations can be updated with safeload during each audio
frame. The target address offset of 1 is used because the write
address is calculated relative to the address of the data, which
starts at Address 0x0001. Therefore, to update a parameter at
Address 0x000A, the target address is 0x0009.
Address 0x0007 designates the number of words to be written
into the parameter RAM during the safeload. A biquad filter
uses all five safeload data addresses. A simple mono gain cell
uses only one safeload data address. Writing to Address 0x0007
also triggers the safeload write to occur in the next audio frame.
The safeload mechanism is software based and executes once
per audio frame. Therefore, system designers must take care
when designing the communication protocol. A delay equal to
or greater than the sampling period (the inverse of sampling
frequency) is required between each safeload write. A sample
rate of 48 kHz equates to a delay of at least 21 μs. If this delay
is not observed, the downloaded data is corrupted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX6174BASA+ | IC VREF SERIES PREC 4.096V 8SOIC |
| GSC06DRXI-S734 | CONN EDGECARD 12POS DIP .100 SLD |
| 0982660987 | CBL 29PS 0.5MM JMPR TYPE A 1.18" |
| SRR5028-680Y | INDUCTOR POWER 68UH 0.62A SMD |
| ADN8831ACPZ-REEL7 | IC THERMO COOLER CTRLR 32LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADAU1781Z | 功能描述:BOARD EVAL FOR ADAU1781 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADAU1962AZ | 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADAU1962A - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:Eval Board for ADAU1962A |
| EVAL-ADAU1966AZ | 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADAU1962A - Boxed Product (Development Kits) |
| EVAL-ADAU1966Z | 功能描述:BOARD EVAL FOR ADAU1966 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-ADAU1966Z | 制造商:Analog Devices 功能描述:ADAU1966, DAC, SIGMA DELTA, SPI, I2C, EV |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。