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| 型號： | EVAL-ADAU1761Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADAU1761 |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻編解碼器 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1761 |
| 主要屬性： | 立體聲，24 位，8 ~ 96 kHz 采樣率，GUI 工具 |
| 次要屬性： | I²C 和 GPIO 接口，2 差分和 1 個立體聲單端模擬輸入和輸出 |
| 已供物品： | 2 個板，線纜，CD |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADAU1761BCPZ-RL-ND - IC SIGMADSP CODEC PLL 32LFCSP ADAU1761BCPZ-R7-ND - IC SIGMADSP CODEC PLL 32LFCSP ADAU1761BCPZ-ND - IC SIGMADSP CODEC PLL 32LFCSP |
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ADAU1761
Rev. C | Page 45 of 92
DSP CORE
SIGNAL PROCESSING
The ADAU1761 is designed to provide all audio signal processing
functions commonly used in stereo or mono low power record
and playback systems. The signal processing flow is designed
using the SigmaStudio software, which allows graphical entry
and real-time control of all signal processing functions.
Many of the signal processing functions are coded using full,
56-bit, double-precision arithmetic data. The input and output
word lengths of the DSP core are 24 bits. Four extra headroom
bits are used in the processor to allow internal gains of up to
24 dB without clipping. Additional gains can be achieved by
initially scaling down the input signal in the DSP signal flow.
ARCHITECTURE
The DSP core consists of a simple 28-/56-bit multiply-accumulate
(MAC) unit with two sources: a data source and a coefficient
source. The data source can come from the data RAM, a ROM
table of commonly used constant values, or the audio inputs to
the core. The coefficient source can come from the parameter
RAM or from a ROM table of commonly used constant values.
The two sources are multiplied in a 28-bit fixed-point multiplier
and then the signal is input to the 56-bit adder; the result is usually
stored in one of three 56-bit accumulator registers. The accumu-
lators can be output from the core (in 28-bit format) or can
optionally be written back into the data or parameter RAMs.
COEFFICIENT SOURCE
(PARAMETER RAM,
ROM CONSTANTS)
DATA OPERATIONS
(ACCUMULATORS (3), dB CONVERSION,
BIT OPERATORS, BIT SHIFTER, ...)
DATA SOURCE
(DATA RAM,
ROM CONSTANTS,
AUDIO INPUTS)
OUTPUTS
TRUNCATOR
56
28
56
07
68
0-
0
67
Figure 67. Simplified DSP Core Architecture
PROGRAM COUNTER
The execution of instructions in the core is governed by a program
counter, which sequentially steps through the addresses of the
program RAM. The program counter starts every time that a
new audio frame is clocked into the core. SigmaStudio inserts
a jump-to-start command at the end of every program. The
program counter increments sequentially until it reaches this
command and then jumps to the program start address and
waits for the next audio frame to clock into the core.
FEATURES
The SigmaDSP core was designed specifically for audio processing
and therefore includes several features intended for maximizing
efficiency. These include hardware decibel conversion and audio-
specific ROM constants.
STARTUP
Before the DSPRUN bit is set or any settings are written to the
parameter RAM, the DSP core must be enabled by setting the
DSPEN bit in Register R61 (Address 0x40F5).
The following steps should be performed every time that a new
program is loaded to the SigmaDSP core, or any time that the
DSPRUN bit is disabled and reenabled.
1.
Set the DSPSR[3:0] bits in Register R57 (Address 0x40EB)
to 1111 (none).
2.
Set the DSPRUN bit in Register R62 (Address 0x40F6) to 0.
3.
Download the rest of the registers, the program RAM, and
the parameter RAM.
4.
Set the DSPRUN bit in Register R62 to 1.
5.
Set the DSPSR[3:0] bits in Register R57 to the operational
setting (default value is 0001).
Changing any register setting or RAM can cause pops and
clicks on the analog outputs. To avoid these pops and clicks,
mute the appropriate outputs using Register R29 to Register R32
(Address 0x4023 to Address 0x4026). Unmute the analog out-
puts after the startup procedure is completed.
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參數(shù)描述 |
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| EVAL-ADAU1781Z | 功能描述:BOARD EVAL FOR ADAU1781 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADAU1962AZ | 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADAU1962A - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:Eval Board for ADAU1962A |
| EVAL-ADAU1966AZ | 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADAU1962A - Boxed Product (Development Kits) |
| EVAL-ADAU1966Z | 功能描述:BOARD EVAL FOR ADAU1966 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-ADAU1966Z | 制造商:Analog Devices 功能描述:ADAU1966, DAC, SIGMA DELTA, SPI, I2C, EV |
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