參數(shù)資料
型號(hào): EVAL-ADAU1761Z
廠商: Analog Devices Inc
文件頁數(shù): 63/92頁
文件大小: 0K
描述: BOARD EVAL FOR ADAU1761
標(biāo)準(zhǔn)包裝: 1
系列: SigmaDSP®
主要目的: 音頻編解碼器
嵌入式: 是,DSP
已用 IC / 零件: ADAU1761
主要屬性: 立體聲,24 位,8 ~ 96 kHz 采樣率,GUI 工具
次要屬性: I²C 和 GPIO 接口,2 差分和 1 個(gè)立體聲單端模擬輸入和輸出
已供物品: 2 個(gè)板,線纜,CD
產(chǎn)品目錄頁面: 776 (CN2011-ZH PDF)
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ADAU1761
Rev. C | Page 66 of 92
R19: ADC Control, 16,409 (0x4019)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
ADCPOL
HPF
DMPOL
DMSW
INSEL
ADCEN[1:0]
Table 53. ADC Control Register
Bits
Bit Name
Description
6
ADCPOL
Invert input polarity.
0 = normal (default).
1 = inverted.
5
HPF
ADC high-pass filter select. At 48 kHz, f3dB = 2 Hz.
0 = off (default).
1 = on.
4
DMPOL
Digital microphone data polarity swap.
0 = invert polarity.
1 = normal (default).
3
DMSW
Digital microphone channel swap. Normal operation sends the left channel on the rising edge of the clock and
the right channel on the falling edge of the clock.
0 = normal (default).
1 = swap left and right channels.
2
INSEL
Digital microphone input select. When asserted, the on-chip ADCs are off, BCLK is master at 128 × fS, and
ADC_SDATA is expected to have left and right channels interleaved.
0 = digital microphone inputs off, ADCs enabled (default).
1 = digital microphone inputs enabled, ADCs off.
[1:0]
ADCEN[1:0]
ADC enable.
Setting
ADCs Enabled
00
Both off (default)
01
Left on
10
Right on
11
Both on
R20: Left Input Digital Volume, 16,410 (0x401A)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LADVOL[7:0]
Table 54. Left Input Digital Volume Register
Bits
Bit Name
Description
[7:0]
LADVOL[7:0]
Controls the digital volume attenuation for left channel inputs from either the left ADC or the left digital
microphone input. Each bit corresponds to a 0.375 dB step with slewing between settings. See Table 94 for a
complete list of the volume settings.
Setting
Volume Attenuation
00000000
0 dB (default)
00000001
0.375 dB
00000010
0.75 dB
11111110
95.25 dB
11111111
95.625 dB
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