參數(shù)資料
型號: EVAL-ADAU1761Z
廠商: Analog Devices Inc
文件頁數(shù): 33/92頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADAU1761
標準包裝: 1
系列: SigmaDSP®
主要目的: 音頻編解碼器
嵌入式: 是,DSP
已用 IC / 零件: ADAU1761
主要屬性: 立體聲,24 位,8 ~ 96 kHz 采樣率,GUI 工具
次要屬性: I²C 和 GPIO 接口,2 差分和 1 個立體聲單端模擬輸入和輸出
已供物品: 2 個板,線纜,CD
產(chǎn)品目錄頁面: 776 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: ADAU1761BCPZ-RL-ND - IC SIGMADSP CODEC PLL 32LFCSP
ADAU1761BCPZ-R7-ND - IC SIGMADSP CODEC PLL 32LFCSP
ADAU1761BCPZ-ND - IC SIGMADSP CODEC PLL 32LFCSP
ADAU1761
Rev. C | Page 39 of 92
The R/W bit determines the direction of the data. A Logic 0 on
the LSB of the first byte means that the master will write infor-
mation to the peripheral, whereas a Logic 1 means that the
master will read information from the peripheral after writing
the subaddress and repeating the start address. A data transfer
takes place until a stop condition is encountered. A stop
condition occurs when SDA transitions from low to high while
SCL is held high.
shows the timing of an I2C write,
and
shows an I2C read.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the ADAU1761 immediately
jumps to the idle condition. During a given SCL high period,
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADAU1761 does
not issue an acknowledge and returns to the idle condition.
If the user exceeds the highest subaddress while in autoincrement
mode, one of two actions is taken. In read mode, the ADAU1761
outputs the highest subaddress register contents until the master
device issues a no acknowledge, indicating the end of a read. A
no acknowledge condition is where the SDA line is not pulled
low on the ninth clock pulse on SCL. If the highest subaddress
location is reached while in write mode, the data for the invalid
byte is not loaded into any subaddress register, a no acknowledge
is issued by the ADAU1761, and the part returns to the idle
condition.
R/W
0
SCL
SDA
(CONTINUED)
SCL
(CONTINUED)
11
1
ADDR0
ADDR1
0
START BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
DATA BYTE 1
ACK BY
ADAU1761
ACK BY
ADAU1761
ACK BY
ADAU1761
ACK BY
ADAU1761
STOP BY
MASTER
07
68
0-
03
2
Figure 49. I2C Write to ADAU1761 Clocking
R/W
SCL
SDA
(CONTINUED)
SCL
(CONTINUED)
SDA
(CONTINUED)
SCL
(CONTINUED)
START BY
MASTER
FRAME 2
SUBADDRESS BYTE 1
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
CHIP ADDRESS BYTE
FRAME 1
CHIP ADDRESS BYTE
FRAME 5
READ DATA BYTE 1
ACK BY
ADAU1761
ACK BY
ADAU1761
ACK BY
ADAU1761
ACK BY
ADAU1761
STOP BY
MASTER
ACK BY
MASTER
REPEATED
START BY MASTER
R/W
0
76
80
-03
3
ADDR0
ADDR1
01
1
0
01
1
0
Figure 50. I2C Read from ADAU1761 Clocking
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