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參數(shù)資料
| 型號： | EDX5116ABSE-2A-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits XDR DRAM (32M words ?16 bits) |
| 中文描述： | 32M X 16 RAMBUS, PBGA104 |
| 封裝： | LEAD FREE, FBGA-104 |
| 文件頁數(shù)： | 62/78頁 |
| 文件大?。?/td> | 3611K |
| 代理商： | EDX5116ABSE-2A-E |
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Preliminary Data Sheet E0643E30 (Ver. 3.0)
62
EDX5116ABSE
Timing Characteristics
Table 16 summarizes all timing parameters that characterize
this memory component. The only exceptions are the core
timing parameters that are speed-bin dependent. Refer to the
Timing Parameters
section for more information.
The first section of parameters pertains to the timing of the
DQ pins when driving read data.
The second section of parameters is concerned with the tim-
ing for the serial interface signals when driving register read
data.
The third section of parameters is concerned with the time
intervals needed by the interface to transition between power
states.
Timing Parameters
Table 17 summarizes the timing parameters that characterize
the core logic of this memory component. These timing
parameters will vary as a function of the component’s speed
bin. The four sections deal with the timing intervals between
packets with, respectively, row-row commands, row-column
commands, column-column commands, and column-row
commands.
Table 16
Timing Characteristics
Symbol
Parameter and Other Conditions
Minimum
Maximum
Units
Figure(s)
t
Q,DQ
DRSL DQ output delay (variation across 16 Q bits on each DQ pin)
from drive points - output delay @ 2.500 ns
>
t
CYCLE
≥
2.000 ns
@ 3.333 ns
>
t
CYCLE
≥
2.500 ns
@ 3.830 ns
≥
t
CYCLE
≥
3.333 ns
-0.052
-0.065
-0.080
+0.052
+0.065
+0.080
ns
ns
ns
Figure 51
t
QOFF,DQ
DRSL DQ output delay offset (a fixed value for all 16 Q bits on each
DQ pin) from drive points - output delay
0.000
+0.200
t
CYCLE
Figure 51
t
OR,DQ
, t
OF,DQ
DRSL DQ output - rise and fall times (20%-80%).
0.020
0.040
t
CYCLE
Figure 51
t
Q,SI
Serial SCK-to-SDO output delay @ C
LOAD,MAX
= 15 pF
2
15
ns
Figure 53
t
P,SI
Serial SDI-to-SDO propagation delay @ C
LOAD,MAX
= 15 pF
-
15
ns
Figure 53
t
OR,SI
, t
OF,SI
Serial SDO output rise/fall (20%-80%) @ C
LOAD,MAX
= 15 pF
-
10
ns
Figure 53
t
PDN-ENTRY
Time for power state to change after PDN entry
-
16
t
CYCLE
Figure 36
t
PDN-EXIT
Time for power state to change after PDN exit
0
-
t
CYCLE
Figure 36
Table 17
Timing Parameters
Symbol
Parameter and Other Conditions
Min
(A)
Min
(B)
Min
(C)
Units
Figure(s)
t
RC
Row-cycle time: interval between successive t
RC
ROWA-ACT or ROWP-REFA or t
RC-R, 2tCC
= t
RCD-R
+ t
CC
+ t
RDP
+ t
RPa
ROWP-REFI activate commands to the t
RC-W 2tCC, noERAW
= t
RCD-W
+ t
CC
+ t
WRP
+ t
RPa
same bank. t
RC-W 2tCC, ERAW
= t
RCD-W
+ t
CC
+ t
WRP
+ t
RPa
16
16
19
23
20
20
24
28
24
24
24
28
t
CYCLE
Figure 4 -
Figure 7
t
RAS
Row-asserted time: interval between a ROWA-ACT or ROWP-REFA or ROWP-REFI activate
command and a ROWP-PRE or ROWP-REFP precharge command to the same bank.
Note that t
RAS,MAX
is 64 us for all timing bins.
10
13
17
t
CYCLE
Figure 4 -
Figure 7
t
RP
Row-precharge time: interval between a ROWP-PRE or ROWP-REFP precharge command
and a ROWA-ACT or ROWP-REFA or ROWP-REFI activate command to the same bank.
6
7
7
t
CYCLE
Figure 4 -
Figure 7
t
PP
Precharge-to-precharge time: interval between successive ROWP- t
PRE or ROWP-REFP precharge commands to different banks. t
PPP
4
1
4
1
4
1
t
CYCLE
Figure 4 -
Figure 7
t
RR
Row-to-row time: interval between ROWA-ACT or ROWP- t
RR
REFA or ROWP-REFI activate commands to different banks. t
RR-Dc
4
4
4
4
4
4
t
CYCLE
Figure 4 -
Figure 7
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| EDX5116ABSE-3A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
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| EDX5116ABSE-3C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
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