參數(shù)資料
型號(hào)： EDX5116ABSE-2A-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits XDR DRAM (32M words ?16 bits)
中文描述： 32M X 16 RAMBUS, PBGA104
封裝： LEAD FREE, FBGA-104
文件頁(yè)數(shù)： 32/78頁(yè)
文件大?。?/td> 3611K
代理商： EDX5116ABSE-2A-E
Preliminary Data Sheet E0643E30 (Ver. 3.0)
32
EDX5116ABSE
Register Operations
Serial Transactions
The serial interface consists of five pins. This includes RST,
SCK, CMD, SDI, and SDO. SDO uses CMOS signaling levels.
The other four pins use RSL signaling levels. RST, CMD, SDI,
and SDO use a timing window which surrounds the falling
edge of SCK). The RST pin is used for initialization.
Figure 14 and Figure 15 show examples of a serial write trans-
action and a serial read transaction. Each transaction starts on
cycle S
4
and requires 32 SCK edges. The next serial transaction
can begin on cycle S
36
. SCK does not need to be asserted if
there is no transaction.
Serial Write Transaction
The serial device write transaction in Figure 14 begins with the
Start[3:0] field. This consists of bits “1100” on the CMD pin.
This indicates to the XDR DRAM that the remaining 28 bits
constitute a serial transaction.
The next two bits are the SCMD[1:0] field. This field contains
the serial command, the bits 00 in the case of a serial device
write transaction.
The next eight bits are “00” and the SID[5:0] field. This field
contains the serial identification of the device being accessed.
The next eight bits are the SADR[7:0] field. This field contains
the serial address of the control register being accessed.
A single bit “0” follows next. This bit allows one cycle for the
access time to the control register.
The next eight bits on the CMD pin is the SWD[7:0] field. This
is the write data that is placed into the selected control register.
A final bit “0” is driven on the CMD pin to finish the serial
write transaction.
A serial broadcast write is identical except that the contents of
the SID[5:0] field in the transaction is ignored and all devices
preform the register write. The SDI and SDO pins are not
used during either serial write transaction.
Serial Read Transaction
The serial device read transaction in Figure 15 begins with the
Start[3:0] field. This consists of bits “1100” on the CMD pin.
This indicates that the remaining 28 bits constitute a serial
transaction.
The next two bits are the SCMD[1:0] field. This field contains
the serial command, and the bits “10” in the case of a serial
device read transaction.
The next eight bits are “00” and the SID[5:0] field. This field
contains the serial identification of the device being accessed.
The next eight bits are the SADR[7:0] field and contain the
serial address of the control register being accessed.
A single bit “0” follows next. This bit allows one cycle for the
access time to the control register and time to turn on the SDO
output driver.
The next eight bits on the CMD pin are the sequence
“00000000”. At the same time, the eight bits on the SDO pin
are the SRD[7:0] field. This is the read data that is accessed
from the selected control register. Note the output timing con-
vention here: bit SRD[7] is driven from a time t
Q,SI,MAX
after
edge S
26
to a time t
Q,SI,MIN
after edge S
27
. The bit is sampled
in the controller by the edge S
27
A final bit “0” is driven on the CMD pin to finish the serial
read transaction.
A serial forced read is identical except that the contents of the
SID[5:0] field in the transaction is ignored and all devices pre-
form the register read. This is used for device testing.
Figure 16 shows the response of a DRAM to a serial device
read transaction when its internal SID[5:0] register field doesn’t
match the SID[5:0] field of the transaction. Instead of driving
read data from an internal register for cycle edges S
27
through
S
34
on the SDO output pin, it passes the input data from the
SDI input pin to the SDO output pin during this same period.
Table 8
SCMD Field Encoding Summary
SCMD
[1:0]
Command
Description
00
SDW
Serial device write — one device is written, the one whose SID[5:0] register matches the SID[5:0] field of the transaction.
01
SBW
Serial broadcast write — all devices are written, regardless of the contents of the SID[5:0] register and the SID[5:0] transaction field
10
SDR
Serial device read — one device is read, the one whose SID[5:0] register matches the SID[5:0] field of the transaction.
11
SFR
Serial forced read — all devices are read, regardless of the contents of the SID[5:0] register and the SID[5:0] transaction field
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