參數(shù)資料
型號(hào): EDX5116ABSE-2A-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 512M bits XDR DRAM (32M words ?16 bits)
中文描述: 32M X 16 RAMBUS, PBGA104
封裝: LEAD FREE, FBGA-104
文件頁(yè)數(shù): 6/78頁(yè)
文件大?。?/td> 3611K
代理商: EDX5116ABSE-2A-E
Preliminary Data Sheet E0643E30 (Ver. 3.0)
6
EDX5116ABSE
List of Figures
XDR DRAM Device Write and Read Transactions .....3
512Mb (8x4Mx16) XDR DRAM Block Diagram ..........9
Request Packet Formats ..............................................11
ACT-, RD-, WR-, PRE-to-ACT Packet Interactions . 16
ACT-, RD-, WR-, PRE-to-RD Packet Interactions ... 17
ACT-, RD-, WR-, PRE-to-WR Packet Interactions ... 18
ACT-, RD, WR-, PRE-to-PRE Packet Interactions .. 19
Request Scheduling Examples ................................... 21
Write Transactions .....................................................23
Read Transactions ......................................................25
Interleaved Transactions ............................................27
Write/Read Interaction ..............................................29
Propagation Delay ...................................................... 31
Serial Write Transaction .............................................33
Serial Read Transaction — Selected DRAM ..............33
Serial Read Transaction — Non-selected DRAM .....33
Serial Identification (SID) Register ............................34
Configuration (CFG) Register ....................................35
Power Management (PM) Register ............................35
Write Data Serial Load (WDSL) Control Register .....35
RQ Scan High (RQH) Register .................................36
RQ Scan Low (RQL) Register ....................................36
Refresh Bank (REFB) Control Register .....................36
Refresh High (REFH) Row Register .........................37
Refresh Middle (REFM) Row Register .....................37
Refresh Low (REFL) Row Register ...........................37
IO Configuration (IOCFG) Register ..........................37
Current Calibration 0 (CC0) Register ........................ 38
Current Calibration 1 (CC1) Register ......................... 38
Read Only Memory 0 (ROM0) Register .................... 38
Read Only Memory 1 (ROM1) Register .................... 38
TEST Register ............................................................ 39
Delay (DLY) Control Register ................................... 39
Refresh Transactions ..................................................41
Calibration Transactions ............................................ 43
Power State Management .......................................... 45
Serial Interface System Topology .............................. 46
Initialization Timing for XDR DRAM[k] Device .... 46
Multiplexers for Dynamic Width Control .................. 50
D-to-S and S-to-Q Mapping for Dynamic Width Control
51
Byte Mask Logic ........................................................ 52
Write-Masked (WRM) Transaction Example ........... 53
Write/Read Interaction — No ERAW Feature ......... 54
Write/Read Interaction — ERAW Feature ............... 54
XDR DRAM Block Diagram with Bank Sets .......... 55
Simultaneous Activation — tRR-D Cases ................. 56
Simultaneous Precharge — tPP-D Cases .................. 57
Clocking Waveforms .................................................. 64
RSL RQ Receive Waveforms ..................................... 65
DRSL DQ Receive Waveforms .................................. 67
DRSL DQ Transmit Waveforms ................................ 69
Serial Interface Receive Waveforms ........................... 70
Serial Interface Transmit Waveforms .........................71
Equivalent Circuits for Package Parasitic ................. 73
CSP x16 Package - Pin Numbering (top view) .......... 75
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