參數(shù)資料
型號： EDX5116ABSE-2A-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits XDR DRAM (32M words ?16 bits)
中文描述： 32M X 16 RAMBUS, PBGA104
封裝： LEAD FREE, FBGA-104
文件頁數(shù)： 28/78頁
文件大?。?/td> 3611K
代理商： EDX5116ABSE-2A-E
Preliminary Data Sheet E0643E30 (Ver. 3.0)
28
EDX5116ABSE
Read/Write Interaction
The previous section described overlapped read transactions
and overlapped write transactions in isolation. This section will
describe the interaction of read and write transactions and the
spacing required to avoid channel and core resource conflicts.
Figure 12 shows a timing diagram (top) for the first case, a
write transaction followed by a read transaction. Two COL
packets with WR commands are presented on cycles T
0
and
T
2
. The write data packets are presented a time t
CWD
later on
cycles T
4
and T
6
. The device requires a time t
WR
after the sec-
ond COL packet with a WR command before a COL packet
with a RD command may be presented. Two COL packets
with RD commands are presented on cycles T
11
and T
13
. The
read data packets are returned a time t
CAC
later on cycles T
17
and T
19
. The time t
WR
is required for turning around internal
bidirectional interconnections (inside the device). This time
must be observed regardless of whether the write and read
commands are directed to the same bank or different banks. A
gap t
WR-BUB,XDRDRAM
will appear on the DQ bus between the
end of the D(a2) packet and the beginning of the Q(b1) packet
(measured at the appropriate packet reference points). The size
of this gap can be evaluated by calculating the difference
between cycles T
2
and T
17
using the two timing paths:
t
WR-BUB,XDRDRAM
≤
t
WR
+ t
CAC
- t
CWD
- t
CC
In this example, the value of t
WR-BUB,XDRDRAM
is greater than
its minimum value of t
WR-BUB,XDRDRAM,MIN
. The values of
t
RW
and
t
CAC
are equal to their minimum values.
In the second case, the timing diagram displayed at the bottom
of Figure 12 illustrates a read transaction followed by a write
transaction. Two COL packets with RD commands are pre-
sented on cycles T
0
and T
2
. The read data packets are returned
a time t
CAC
later on cycles T
6
and T
8
. The device requires a
time t
RW
after the second COL packet with a RD command
before a COL packet with a WR command may be presented.
Two COL packets with WR commands are presented on cycles
T
10
and T
12
. The write data packets are presented a time t
CWD
later on cycles T
13
and T
15
. The time t
RW
is required for turn-
ing around the external DQ bidirectional interconnections
(outside the device). This time must be observed regardless
whether the read and write commands are directed to the same
bank or different banks. The time t
RW
depends upon four
timing parameters, and may be evaluated by calculating the dif-
ference between cycles T
2
and T
13
using the two timing paths:
t
RW
+ t
CWD
= t
CAC
+ t
CC
+ t
RW-BUB,XDRDRAM
or
t
RW
= (t
CAC
- t
CWD
)+ t
CC
+ t
RW-BUB,XDRDRAM
In this example, the values of t
RW
, t
CAC
,
t
CWD
, t
CC
, and
t
RW-
BUB,XDRDRAM
are equal to their minimum values.
Propagation Delay
Figure 13 shows two timing diagrams that display the system-
level timing relationships between the memory component and
the memory controller.
The timing diagram at the top of the figure shows the case of a
write-read-write command and data at the memory compo-
nent. In this case, the timing will be identical to what has
already been shown in the previous sections; i.e. with all timing
measured at the pins of the memory component. This timing
diagram was produced by merging portions of the top and bot-
tom timing diagrams in Figure 12.
The example shown is that of a single COL packet with a write
command, followed by a single COL packet with a read com-
mand, followed by a second COL packet with a write com-
mand. These accesses all assume a page-hit to an open bank.
A timing interval t
WR
is required between the first WR com-
mand and the RD command, and a timing interval t
RW
is
required between the RD command and the second WR com-
mand. There is a write data delay t
CWD
between each WR com-
mand and the associated write data packet D. There is a read
data delay t
CAC
between the RD command and the associated
read data packet Q. In this example, all timing parameters have
assumed their minimum values except t
WR-BUB,XDRDRAM
.
The lower timing diagram in the figure shows the case where
timing skew is present between the memory controller and the
memory component. This skew is the result of the propagation
delay of signal wavefronts on the wires carrying the signals.
The example in the lower diagram assumes that there is a prop-
agation delay of t
PD-RQ
along both the RQ wires and the
CFM/CFMN clock wires between the memory controller and
the memory component (the value of t
PD-RQ
used here is
1*t
CYCLE
). Note that in an actual system the t
PD-RQ
value will
be different for each memory component connected to the RQ
wires.
In addition, it is assumed that there is a propagation delay t
PD-
D
along the DQ/DQN wires between the memory controller
and the memory component (the direction in which write data
travels, and it is assumed that there is the same propagation
delay t
PD-Q
along the DQ/DQN wires between the memory
component and the memory controller (the direction in which
read data travels). The sum of these two propagation delays is
also denoted by the timing parameter t
PD,CYC
= t
PD-D
+t
PD-Q
.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDX5116ABSE-3A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits)
EDX5116ABSE-3B-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits)
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EDX5116ABSE-4C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits)
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