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參數(shù)資料
| 型號(hào)： | EDE5104AJSE |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | EDE5104AJSE |
| 中文描述： | EDE5104AJSE |
| 文件頁數(shù)： | 72/77頁 |
| 文件大?。?/td> | 604K |
| 代理商： | EDE5104AJSE |
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EDE5104AJSE, EDE5108AJSE, EDE5116AJSE
Data Sheet E1043E40 (Ver. 4.0)
72
Input Clock Frequency Change during Precharge Power Down
DDR2 SDRAM input clock frequency can be changed under following condition:
DDR2 SDRAM is in precharged power-down mode. ODT must be turned off and CKE must be at logic low level.
A minimum of 2 clocks must be waited after CKE goes low before clock frequency may change. SDRAM input clock
frequency is allowed to change only within minimum and maximum operating frequency specified for the particular
speed grade. During input clock frequency change, ODT and CKE must be held at stable low levels.
Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power-down
may be exited and DLL must be RESET via EMRS after precharge power-down exit. Depending on new clock
frequency an additional MRS command may need to be issued to appropriately set the WR, CL and soon. During
DLL relock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock
frequency.
Clock Frequency Change in Precharge Power Down Mode
CK
CKE
T0
T4
Tx+1
Ty
Ty+1
Ty+2
T1
T2
Tx
/CK
Ty+3
Tz
tRP
tXP
tAOFD
Stable new clock
before power down exit
ODT is off during
DLL RESET
Minmum 2 clocks
required before
changing frequency
ODT
Command
Ty+4
NOP
NOP
NOP
NOP
DLL
RESET
NOP
Valid
200 clocks
Frequency change
Burst Interruption
Interruption of a burst read or write cycle is prohibited.
No Operation Command [NOP]
The no operation command should be used in cases when the DDR2 SDRAM is in an idle or a wait state. The
purpose of the no operation command is to prevent the DDR2 SDRAM from registering any unwanted commands
between operations. A no operation command is registered when /CS is low with /RAS, /CAS, and /WE held high at
the rising edge of the clock. A no operation command will not terminate a previous operation that is still executing,
such as a burst read or write cycle.
Deselect Command [DESL]
The deselect command performs the same function as a no operation command. Deselect Command occurs when
/CS is brought high at the rising edge of the clock, the /RAS, /CAS, and /WE signals become don’t cares.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDE5108AJBG | 512M bits DDR2 SDRAM |
| EDE5108AJBG-6E-E | 512M bits DDR2 SDRAM |
| EDE5108AJBG-8E-E | 512M bits DDR2 SDRAM |
| EDE5116AJBG | 512M bits DDR2 SDRAM |
| EDE5116AJBG-6E-E | 512M bits DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE5104AJSE-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AJSE-8E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104GASA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR-II SDRAM |
| EDE5104GASA-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR-II SDRAM |
| EDE5104GASA-5A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR-II SDRAM |
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