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參數(shù)資料
| 型號： | EDE5104AJSE |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | EDE5104AJSE |
| 中文描述： | EDE5104AJSE |
| 文件頁數(shù)： | 39/77頁 |
| 文件大?。?/td> | 604K |
| 代理商： | EDE5104AJSE |
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EDE5104AJSE, EDE5108AJSE, EDE5116AJSE
Data Sheet E1043E40 (Ver. 4.0)
39
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon
returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self-
refresh operation and is automatically re-enabled upon exit of self-refresh operation. Any time the DLL is enabled
(and subsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the
internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a
violation of the tAC or tDQSCK parameters.
EMRS (2) Programming
*1
The extended mode register (2) controls refresh related features. The default value of the extended mode
register (2) is not defined, therefore the extended mode register (2) must be written after power-up for proper
operation. The extended mode register (2) is written by asserting low on CS, /RAS, /CAS, /WE, high on BA1 and low
on BA0, while controlling the states of address pins A0 to A13. The DDR2 SDRAM should be in all bank precharge
with CKE already high prior to writing into the extended mode register (2). The mode register set command cycle
time (tMRD) must be satisfied to complete the write operation to the extended mode register (2). Mode register
contents can be changed using the same command and clock cycle requirements during normal operation as long
as all banks are in the precharge state.
Address field
Extended mode register (2)
0*
1
0*
1
SRF
A13
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
BA1 BA0
A12
A7
0
1
High Temperature
Self-refresh rate
Enable
Disable
Enable
Note: 1 The rest bits in EMRS (2) is reserved for future use and all bits in EMRS (2) except A7, BA0 and BA1
must be programmed to 0 when setting the extended mode register (2) during initialization.
EMRS(2)
EMRS (3) Programming: Reserved
*1
Extended Mode Register(3)
0*
1
1
1
Address Field
A13
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA1 BA0
A12
Note : 1. EMRS (3) is reserved for future use and all bits except BA0 and BA1 must be programmed
to 0 when setting the mode register during initialization.
EMRS (3)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDE5108AJBG | 512M bits DDR2 SDRAM |
| EDE5108AJBG-6E-E | 512M bits DDR2 SDRAM |
| EDE5108AJBG-8E-E | 512M bits DDR2 SDRAM |
| EDE5116AJBG | 512M bits DDR2 SDRAM |
| EDE5116AJBG-6E-E | 512M bits DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE5104AJSE-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AJSE-8E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104GASA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR-II SDRAM |
| EDE5104GASA-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR-II SDRAM |
| EDE5104GASA-5A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR-II SDRAM |
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