參數(shù)資料
型號： EDE5104AJSE
廠商： Elpida Memory, Inc.
英文描述： EDE5104AJSE
中文描述： EDE5104AJSE
文件頁數(shù)： 26/77頁
文件大?。?/td> 604K
代理商： EDE5104AJSE
EDE5104AJSE, EDE5108AJSE, EDE5116AJSE
Data Sheet E1043E40 (Ver. 4.0)
26
DM, UDM and LDM (input pins)
DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input
data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading.
For
×
8 configuration, DM function will be disabled when RDQS function is enabled by EMRS.
In
×
16 configuration, UDM controls upper byte (DQ8 to DQ15) and LDM controls lower byte (DQ0 to DQ7). In this
datasheet, DM represents UDM and LDM.
DQ (input/output pins)
Bi-directional data bus.
DQS, /DQS UDQS, /UDQS, LDQS, /LDQS (input/output pins)
Output with read data, input with write data for source synchronous operation. Edge-aligned with read data,
centered in write data. Used to capture write data. /DQS can be disabled by EMRS.
In
×
16 configuration, UDQS, /UDQS and LDQS, /LDQS control upper byte (DQ8 to DQ15) and lower byte (DQ0 to
DQ7). In this datasheet, DQS represents UDQS and LDQS, /DQS represents /UDQS and /LDQS.
RDQS, /RDQS (output pins)
Differential Data Strobe for READ operation only. DM and RDQS functions are switch able by EMRS. These pins
exist only in
×
8 configuration. /RDQS output will be disabled when /DQS is disabled by EMRS
.
ODT (input pins)
ODT (On Die Termination control) is a registered high signal that enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, RDQS, /RDQS and DM signal for
×
4/
×
8 configurations. For
×
16 configuration, ODT is applied to each DQ, UDQS, /UDQS, LDQS, /LDQS, UDM, and
LDM signal. The ODT pin will be ignored if the Extended Mode Register (EMRS) is programmed to disable ODT.
Any time the EMRS enables the ODT function; ODT may not be driven high until eight clocks after the EMRS has
been enabled.
VDD, VSS, VDDQ, VSSQ (power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
VDDL and VSSDL (power supply)
VDDL and VSSDL are power supply pins for DLL circuits.
VREF (Power supply)
SSTL_18 reference voltage: (0.50
±
0.01)
×
VDDQ
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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