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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 86/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
86
DRAFT COPY
Lucent Technologies Inc.
Software Architecture
(continued)
Registers
Peripheral Register Write-Read Latency
As a consequence of the pipelined IDB, there is a
write-to-read latency for peripheral (off-core) registers.
This latency is automatically compensated by the
DSP16000 assembler.
For all peripheral registers except MIOU registers,
there is a one cycle write-to-read latency. For example:
timer0c=0x00aa
nop
a0h=timer0c
// update timer0c
// inserted by assembler
// returns 0x00aa
In the above example, the
nop
instruction (or any other
instruction that does not read
timer0c
) is needed to
guarantee that the subsequent read of
timer0c
returns
the updated value. To prevent the assembler from
inserting the
nop
, the programmer can insert any
instruction.
For MIOU registers, there is a two instruction cycle
latency before the most recently written MIOU register
(
miwp
0—1
or
morp
0—1
) is returned by a subse-
quent peripheral register read. The assembler auto-
matically inserts one or two nop instructions, as
needed. See the program example below:
morp0=0x00aa
2*nop
a3l=morp0
miwp1=a2h
a2l=0x1234
nop
ar0=miwp1
// update morp0
// inserted by assembler
// returns 0x00aa
// update miwp1
// 1-cycle instruction
// inserted by assembler
Register Overview
DSP16210 registers fall into one of the following cate-
gories:
Directly program-accessible (or register-mapped)
registers are directly accessible in instructions and
are designated with lower-case bold, e.g.,
timer0
.
These registers are summarized in
Figure 23 on
page 87
and in
Table 38 starting on page 88
.
ESIO memory-mapped registers are designated with
upper-case bold, e.g.,
ICR
. These registers are sum-
marized in
Table 39 on page 90
.
MIOU-accessible registers are accessible only by
MIOU commands, i.e., by writing the
mcmd0
or
mcmd1
register, and are designated with upper-
case bold, e.g.,
IBAS0
. These registers are summa-
rized in
Table 40 on page 90
.
DMA-accessible registers are SSIO or PHIF16 data
registers that are accessible only via MIOU DMA in
IORAM locations and are designated with upper-
case bold, e.g.,
PDX
(in). These registers are sum-
marized in
Table 41 on page 90
.
Note:
The program counter (
PC
) is an addressing reg-
ister not accessible to the programmer or
through external pins. The device automatically
controls this register to properly sequence the
instructions.
Figure 23 on page 87
depicts the directly program-
accessible registers of which there are three types:
Data
registers store data either from the result of
instruction execution or from memory. Data registers
become source operands for instructions. This class of
registers also includes postincrement registers whose
contents are added to address registers to form new
addresses.
Control and Status
registers are used to determine
the state of the machine or to set different configura-
tions to control the machine.
Address
registers are used to hold memory location
pointers. In some cases, the user can treat address
registers as general-purpose data registers accessible
by data move instructions.
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