參數(shù)資料
型號： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號處理器
文件頁數(shù)： 150/173頁
文件大?。?/td> 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
150
DRAFT COPY
Lucent Technologies Inc.
Timing Characteristics and Requirements
(continued)
External Memory Interface
(continued)
A = number of DSP clock cycles programmed into the
mwait
register (XATIM, YATIM, IATIM) for the access. In the example depicted in this
drawing, YATIM = 3 and XATIM = 2.
Figure 37. External Memory Data Write Timing Diagram (DENB2 = 0, DENB1 = 0, DENB0 = 0)
Table 106. Timing Characteristics for External Memory Data Write (RWNADV
= 0, DENB
= 0)
RWNADV is bit 3 of the
ioc
register.
DENB is replaced with the DENB[2:0] bit of the
ioc
register that corresponds to the memory segment that is accessed. DENB is DENB2 for
the IO segment, DENB1 for the ERAMHI and ERAMLO segments, and DENB0 for the EROM segment.
WDDLY is bit 10 of the
ioc
register.
T = internal clock period (CLK).
Abbreviated
Reference
t131
t132
t133
t134
Parameter
Condition
Min
Max Unit
Write Overlap (enable low to 3-state)
RWN Advance (RWN high to enable high)
RWN Delay (enable low to RWN low)
Write Data Setup (data valid to RWN high)
—
—
—
—
0
0
0
2
3
—
—
—
—
—
—
T/2
T
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WDDLY
§
= 0
WDDLY
§
= 1 (T × (A – 1)) – 3
—
—
WDDLY
§
= 0
WDDLY
§
= 1
WDDLY
§
= 0
WDDLY
§
= 1
§
(T × (A – 0.5)) – 3
t135
t136
t137
RWN Width (low to high)
Write Address Setup (address valid to RWN low)
Write Data Activation Delay (RWN low to DB active)
(T × A) – 3
0
T/2 – 4
T – 4
—
—
t142
Write Data Deactivation Delay (RWN high to DB
3-state)
ERAMLO
EROM
CKO
AB
RWN
DB
WRITE ADDRESS
READ ADDRESS
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
WRITE DATA
READ
t131
t132
t134
t133
t135
t136
A
= 3
V
OH
V
OL
A
= 2
t137
t142
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