- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377000 > DSP16210 TVS 400W 6.5V UNIDIRECT SMA PDF資料下載
參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 125/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)當(dāng)前第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
125
Signal Descriptions
(continued)
PHIF16 Interface
The PHIF16 interface implements a full 16-bit host
interface to standard microprocessors.
PB[15:0] —
PHIF16
Parallel I/O Data Bus:
Input/Out-
put. This 16-bit bidirectional bus is used to input data
to, or output data from, the PHIF16. It can be config-
ured as an 8-bit external bus where PB[15:8] are 3-
stated.
PCSN —
PHIF16
Peripheral Chip Select Not:
Nega-
tive assertion input. If PCSN is low, the data strobes
PIDS and PODS are enabled. If PCSN is high, the
DSP16210 ignores any activity on PIDS and PODS.
PBSEL — PHIF16 Peripheral Byte Select:
Input. The
assertion level is configurable in software via
PHIFC
[3].
Selects the high or low byte of PDX available for host
accesses (8-bit external mode).
PSTAT — PHIF16 Peripheral Status Register Select:
Input. If a logic 0, the PHIF16 outputs the PDX(out)
register on the PB bus. If a logic 1, the PHIF16 outputs
the contents of the
PSTAT
register on PB[7:0].
PIDS —
PHIF16
Input Data Strobe:
Input. Supports
either Intelor Motorolaprotocols. Configured by the
PHIFC
[PSTROBE] control register bit.
In Intelmode: Negative assertion. PIDS is pulled low
by an external device to indicate that data is available
on the PB bus. The DSP latches data on the PB bus on
the rising edge (low-to-high transition) of PIDS or
PCSN, whichever comes first.
In Motorolamode: PIDS (PRWN) functions as a
read/write strobe. The external device sets PIDS
(PRWN) to a logic 0 to indicate that data is available on
the PB bus (write operation by the external device). A
logic 1 on PIDS (PRWN) indicates an external read
operation by the external device.
PODS —
PHIF16
Output Data Strobe:
Input. Soft-
ware-configurable to support both Inteland Motorola
protocols:
In Intelmode: Negative assertion. When PODS is
pulled low by an external device, the DSP16210 places
the contents of the parallel output register, PDX(out),
onto the PB bus.
In Motorolamode: Software-configurable assertion
level. The external device uses PODS (PDS) as its
data strobe for both read and write operations.
PIBF —
PHIF16
Input Buffer Full:
Output. The asser-
tion level is configurable in software (
PHIFC
[4]). This
flag is cleared after reset, indicating an empty input
register PDX(in). PIBF is set immediately after the ris-
ing edge of PIDS or PCSN, indicating that data has
been latched into the PDX(in) register. When the
DSP16210 reads the contents of this register, emptying
the buffer, this flag is cleared. Configured in software
(
PHIFC
[5]), PIBF can become the logical OR of the
PIBF and POBE flags.
POBE — PHIF16
Output Buffer Empty:
Output. The
assertion level is configurable in software (
PHIFC
[4]).
This flag is set after reset, indicating an empty output
register PDX(out). POBE is set immediately after the
rising edge of PODS or PCSN, indicating that the data
in PDX(out) has been driven onto the PB bus. When
the DSP16210 writes to PDX(out), filling the buffer, this
flag is cleared.
JTAG Test Interface
The JTAG test interface has features that allow pro-
grams and data to be downloaded into the DSP via four
pins. This provides extensive test and diagnostic capa-
bility. In addition, internal circuitry allows the device to
be controlled through the JTAG port to provide on-chip,
in-circuit emulation. Lucent Technologies provides
hardware and software tools to interface to the on-chip
HDS via the JTAG port.
Note:
The DSP16210 provides all JTAG/IEEE1149.1
standard test capabilities including boundary
scan.
TDI — JTAG Test Data Input:
Serial input signal. All
serial-scanned data and instructions are input on this
pin. This pin has an internal pull-up resistor.
TDO — JTAG Test Data Output:
Serial output signal.
Serial-scanned data and status bits are output on this
pin.
TMS — JTAG
Test Mode Select:
Mode control signal
that, when combined with TCK, controls the scan oper-
ations. This pin has an internal pull-up resistor.
TCK — JTAG Test Clock:
Serial shift clock. This signal
clocks all data into the port through TDI, and out of the
port through TDO, and controls the port by latching the
TMS signal inside the state-machine controller.
TRST —
JTAG
TAP Controller Reset:
Negative
assertion. Test reset. When asserted low, resets JTAG
TAP controller. In an application environment, this pin
must be asserted prior to or concurrent with RSTB.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP1627 | TVS 400W 6.5V BIDIRECT SMA |
| DSP1629 | TVS 400W 64V UNIDIRECT SMA |
| DSP16410C | TVS 400W 7.0V UNIDIRECT SMA |
| DSP16410 | 16-bit fixed point DSP with Flash |
| DSP25-16AR | Phase-leg Rectifier Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP1627 | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP1627 Digital Signal Processor |
| DSP1627F32K10IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K10IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K11I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| DSP1627F32K11IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。