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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 12/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
12
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
DSP16210 Architectural Overview
(continued)
Table 1. DSP16210 Block Diagram Legend
(continued)
Internal Boot ROM (IROM)
The DSP16210 includes a boot ROM that contains
hardware development code and boot routines. The
boot routines are available for use by the programmer
and are detailed in
DSP16210 Boot Routines begin-
ning on page 126
.
IORAM and Modular I/O Units (MIOUs)
IORAM storage consists of two 1 Kword banks of mem-
ory, IORAM0 and IORAM1. Each IORAM bank has two
16-bit data and two 10-bit address ports; an IORAM
bank can be shared with the core and a modular I/O
unit (MIOU) to implement a DMA-based I/O system.
IORAM supports concurrent core execution and MIOU
I/O processing.
MIOU0 (controls PHIF16) is attached to IORAM0;
MIOU1 (controls SSIO) is attached to IORAM1. Por-
tions of IORAM not dedicated to I/O processing can be
used as general-purpose data storage.
Placing instructions and Y-memory data in the same
IORAM is not supported and may cause undefined
results.
The IORAMs and MIOUs are described in detail in
Modular I/O Units (MIOUs) beginning on page 42
.
External Memory Interface (EMI)
The EMI connects the DSP16210 to external memory
and I/O devices. It multiplexes the two sets of core
buses (X and Y) onto a single set of external buses—a
16-bit address bus (AB[15:0]) and 16-bit data bus
(DB[15:0]). These external buses can access external
RAM (ERAMHI/ERAMLO), external ROM (EROM), and
memory-mapped I/O space (IO).
The EMI also manages the on-chip IORAM and ESIO
storage. It multiplexes the two sets of core buses onto a
single set of internal buses—a 10-bit address bus
(EAB[9:0]) and 16-bit data bus (EDB[15:0])—to inter-
face to the IORAMs and ESIO memory-mapped regis-
ters.
Instructions can transparently reference external mem-
ory, IORAM, and ESIO storage from either set of core
buses. The EMI automatically translates a single 32-bit
access into two 16-bit accesses and vice versa.
The EMI is described in detail in
External Memory
Interface (EMI) beginning on page 27
.
powerc
PSTAT
sbit
SSDX
(in)
SSDX
(out)
SSIO
SSIOC
TIMER0
timer0
timer0c
TIMER1
timer1
timer1c
XAB
XDB
YAB
YDB
Power Control Register
PHIF16 Status Register
BIO Status/Control Register
SSIO Input Register; Readable by MIOU1
SSIO Output Register; Writable by MIOU1
Simple Serial I/O Unit
SSIO Control Register: Programmed Through MIOU1
Programmable Timer 0
Timer Running Count Register for TIMER0
Timer Control Register for TIMER0
Programmable Timer 1
Timer Running Count Register for TIMER1
Timer Control Register for TIMER1
X-Memory Space Address Bus
X-Memory Space Data Bus
Y-Memory Space Address Bus
Y-Memory Space Data Bus
Symbol
Description
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