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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 63/173頁(yè) |
| 文件大小： | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
Lucent Technologies Inc.
DRAFT COPY
63
Hardware Architecture
(continued)
Power Management
(continued)
STOP Pin
Assertion (active-low) of the STOP pin has the same
effect as setting the NOCK bit in the
powerc
register.
The internal clock (CLK) is synchronously disabled
until STOP is returned high. Once STOP is returned
high, program execution continues from where it left off
without any loss of state. No device reset is
required.
Figure 19 on page 57
illustrates the effect of
STOP on the internal clock.
PLL Powerdown
Clearing PLLEN (bit 15 of the
pllc
register) powers
down the PLL. Do not clear PLLEN if the PLL is
selected as the clock source, i.e., if PLLSEL (bit 14 of
pllc
) is set. See
Clock Synthesis beginning on page 56
for details.
AWAIT Bit of the alf Register
Setting the AWAIT bit of the
alf
register causes the
core to go into the low-power standby mode. In this
mode the peripherals remain active, the PLL remains
active if enabled, and the minimum core circuitry
required to process an incoming interrupt remains
active. Any interrupt returns the core to its previous
state, and program execution continues. As long as the
core is receiving a clock, whether slow or fast, it can be
put into standby mode with the AWAIT bit. Once the
AWAIT bit is set, the STOP pin can be used to stop and
later restart the internal clock, returning to the standby
state. If the internal clock is not running, however, the
AWAIT bit cannot be set.
Power Management Examples
The following examples illustrate the more significant options, not an exhaustive list of options, for reducing power
dissipation. The many options for reducing power include a combination of the following:
I
The choice of clock source to the processor.
I
Whether the user chooses to power down the peripheral units.
I
Whether the internal clock is disabled through hardware or software.
I
The combination of power management modes chosen.
I
Whether or not the PLL or ring oscillator is enabled.
Low-Power Standby Mode with CKI Clock Input.
It is assumed that the PLL is disabled (PLLEN = 0) and the
processor is clocked with a high-speed clock on the CKI pin. Prior to entering low-power standby mode
1
by setting
the AWAIT bit (
alf
[15]), the program reduces power by turning off all the peripherals and holding the CKO pin low.
powerc=0x181f
2*nop
ioc=0x0040
_standby:
/* Prepare for standby mode -- turn off peripherals.*/
/* Wait for it to take effect.
/* Hold CKO low.
/* Set AWAIT bit, stop internal processor clock,... */
/* interrupt circuits active.
/* Needed for bedtime execution. Only standby power */
/* consumed here until interrupt wakes up the device*/
/* User code executes here
/* Turn peripheral units back on
/* Wait for it to take effect.
/* CKO is free-running CLK.
*/
*/
alf=0x8000
nop
nop
nop
...
*/
cont:
*/
*/
*/
*/
powerc=0x0000
2*nop
ioc=0x0000
1. The program exits low-power standby mode when any enabled interrupt occurs. Therefore, it is assumed that interrupts are globally enabled
and at least one interrupt is individually enabled.
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