- 您現(xiàn)在的位置：買(mǎi)賣IC網(wǎng) > PDF目錄377000 > DSP16210 TVS 400W 6.5V UNIDIRECT SMA PDF資料下載
參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 41/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)當(dāng)前第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
41
Hardware Architecture
(continued)
Enhanced Serial I/O Unit (ESIO)
(continued)
Logical channels must be assigned in increasing output
channel start bit order and must not overlap. For exam-
ple, if channel 4 has a start bit of 48 and a sample
length of 4 bits (
OCSB2
[7:0] = 0x30;
OCSL0
[9:8] =
10), then channel 5 must have a start bit value greater
than or equal to 52 (48 + 4).
The ESIO reports an output frame error (EOFE) when
it is processing a valid frame and an output frame sync
is detected before the number of bits in the pro-
grammed frame length (OFRMSZ in
OCR
) have been
transmitted. If an EOFE interrupt occurs, the DSP pro-
gram should reset the output section by writing
OCR
with the ORESET bit set.
When driving output data in frame mode with EDO pro-
grammed as an open-drain device (EDOMD = 1 and
EDOEO = 1), the ESIO samples the EDO pin every
EOBC clock cycle. If the sampled value is not the
intended output value, the ESIO has collided with
another serial bus agent. When a bus collision is
detected, the ESIO asserts the output collision inter-
rupt (ECOL). The DSP program clears ECOL by writing
OCR
with either the ORESET field (bit 4) or the CRE-
SET field (bit 7) set.
Table 14 summarizes the ESIO interrupts. See
Table 7
on page 23
for information on request clearing latency
for these interrupts.
Table 14. ESIO Interrupts
Interrupt
Name
EIBF
Buffer
Description
Cleared By
Input
Full
Simple Mode
(IMODE = 1)
Asserted if a programmed number of input
bits (8 or 16 depending on ISIZE (
ICR
[7]))
have been captured following assertion of
the input frame sync.
Asserted after N nput frames (N= 2, 4, 8,
or 16, depending on IFIR[1:0] (
ICR
[1:0]))
have been received following input section
initialization
. If ICA (
ICR
[2]) remains set,
EIBF is reasserted after every subsequent
Nframes have been received.
Asserted if the input section is processing a
valid frame and an input frame sync is
detected before the number of bits speci-
fied by IFRMSZ[1:0] (
ICR
[11:10]) have
been sampled.
Asserted after the first bit (LSB) has been
output.
Asserted after the first bit (LSB) of the first
frame has been output following output
section initialization
§
. If OCA (
OCR
[2])
remains set, EOBE is reasserted at the
completion of every 2, 4, 8, or 16 frames
depending on OFIR[1:0] (
OCR
[1:0]).
Asserted if the output section is processing
a valid frame and an output frame sync is
detected before the number of bits in the
programmed frame length OFRMSZ[1:0]
(
OCR
[13:12]) have been transmitted.
Asserted if EDO is an open-drain output
(EDOMD (
OCR
[5]) = 1 and EDOEO
(
OCR
[6]) = 1) and the sampled EDO pin
value is not the intended output value.
Any of the following:
I
Device reset.
I
DSP program reads any of
IDMX
0—15
.
I
The DSP program sets the
IRESET field (
ICR
[4]).
Frame Mode
(IMODE = 0)
EIFE
Input
Frame
Error
Frame Mode
(IMODE = 0)
The DSP program sets the
IRESET field (
ICR
[4]).
EOBE
Output
Buffer
Empty
Simple Mode
(OMODE = 1)
Frame Mode
(OMODE = 0)
Any of the following:
I
Device reset.
I
DSP program writes
any of
OMX
0—15
.
I
The DSP program sets the
ORESET field (
OCR
[4]).
EOFE
Output
Frame
Error
Frame Mode
(OMODE = 0)
The DSP program sets the IRE-
SET field.
ECOL
Output
Collision
Frame Mode
(OMODE = 0)
The DSP program sets the
ORESET field (
OCR
[4]) or the
CRESET field (
OCR
[7]).
The DSP program initializes the input section by setting IRESET (
ICR
[4]) and ICA (
ICR
[2]).
This interrupt is disabled in simple mode.
§ The DSP program initializes the output section by setting ORESET (
OCR
[4]) and OCA (
OCR
[2]).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP1627 | TVS 400W 6.5V BIDIRECT SMA |
| DSP1629 | TVS 400W 64V UNIDIRECT SMA |
| DSP16410C | TVS 400W 7.0V UNIDIRECT SMA |
| DSP16410 | 16-bit fixed point DSP with Flash |
| DSP25-16AR | Phase-leg Rectifier Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP1627 | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP1627 Digital Signal Processor |
| DSP1627F32K10IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K10IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K11I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| DSP1627F32K11IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。