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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 23/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
23
Hardware Architecture
(continued)
Interrupts and Trap
(continued)
Clearing Interrupts
Writing a 1 to a bit in the
ins
register causes the corre-
sponding interrupt status bit to be cleared to a logic 0.
This bit is also automatically cleared by the core when
the interrupt is taken, leaving set any other vectored
interrupts that are pending. The MIOU and ESIO inter-
rupt requests can be cleared by particular instructions,
but there is a latency between the instruction execution
and the actual clearing of the interrupt request (see the
section below).
Interrupt Request Clearing Latency
As a consequence of pipeline delay, there is a mini-
mum latency (number of instruction cycles) between
the time a peripheral interrupt clear instruction is exe-
cuted for an MIOU or ESIO interrupt and the corre-
sponding interrupt request is actually cleared. These
latencies are described in Table 7, and are significant
when implementing ISRs or I/O polling loops. See
Modular I/O Units (MIOUs) beginning on page 42
and
Enhanced Serial I/O (ESIO) Unit beginning on page 32
for details on these interrupts.
Table 7. Interrupt Request Clearing Latency
Interrupt Clear Instruction
Subsequent
Instruction
ireturn
Latency
(Cycles)
4
Example
mcmd
0,1
=
ILEN_UP
,
OLEN_UP
,
RESET
(return from interrupt
service routine)
ins
=
REG, MEM
mcmd0=0x4010
4*nop
ireturn
ILEN_UP command clears
MIBF0 request. Four
nop
s
are needed to avoid uninten-
tional re-entry into ISR.
RESET command clears
MIBF1 request and sets
MOBE1 request. Six
nop
s
are needed before MIBF1 bit
in
ins
can be cleared.
r0
is 0xe0000.
a5h = *r0
reads
IDMX0
and clears EIBF
request. Two
nop
s are
needed to avoid uninten-
tional re-entry into ISR.
r5
is 0xe001A (
*r5
is
ICR
).
Bit 4 of
a1h
is one. Four
nop
s
are needed before EIBF or
EIFE bits in
ins
can be
cleared.
r1
is 0xe003A (
*r1
is
OCR
).
Bit 4 of
a4h
is one, causing
the clearing of EOBE, EOFE,
and ECOL requests. Two
nop
s are needed to avoid
unintentional re-entry into
ISR.
r6
is 0xe0020.
*r6 = a3h
writes
OMX0
and clears
EOBE request. Four
nop
s
are needed before EOBE bit
in
ins
can be cleared.
(clear interrupt
pending bit within a
polling routine)
ireturn
6
mcmd1=0x6000
6*nop
ins=0x00008
a0=ins
REG = MEM
(MEM is IDMX
0—15
)
or
MEM = REG
(Bit 4 of REG is one, setting IRESET field.)
(MEM is
ICR
)
(return from interrupt
service routine)
2
a5h=*r0
2*nop
ireturn
ins
=
REG, MEM
(clear interrupt
pending bit within a
polling routine)
ireturn
4
*r5=a1h
4*nop
ins=0x04800
a3=ins
MEM = REG
(MEM is OMX
0—15
)
or
MEM = REG
(Bit 4 or bit 7 of REG is one,
setting ORESET or CRESET field)
(MEM is
OCR
)
(return from interrupt
service routine)
2
*r1=a4h
2*nop
ireturn
ins
=
REG, MEM
(clear interrupt
pending bit within a
polling routine)
4
*r6=a3h
4*nop
ins=0x08000
a3=ins
Key to these columns: REG is any register. MEM is a memory location. ILEN_UP OLEN_UP or RESET is a value (immediate, register con-
tents, or memory location contents) such that bits 15:12 are 0x4, 0x5, or 0x6, respectively.
The
nop
and multiple
nop
instructions in the examples can be replaced by any instruction(s) that takes an equal or greater number of execu-
tion cycles than the
nop
instruction(s).
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