參數(shù)資料
型號： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號處理器
文件頁數(shù)： 130/173頁
文件大?。?/td> 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
130
DRAFT COPY
Lucent Technologies Inc.
DSP16210 Boot Routines
(continued)
Commands
(continued)
Table 81. Command Encoding for Boot Routines
(continued)
0xE9
0xEA
0xEB
0xEE
0xEF
0xF2
0xF4
0xF5
0xF6
0xF7
0x12
0x52
0x92
0x0FFF
PHIF16
EROM
(64K)
16-bit
16-bit
Motorola
active-low
active-high
active-low
active-low
active-high
active-low
active-high
active-low
active-high
active-low
active-high
active-low
active-low
No
64 words
Intel
Motorola
Yes
1 word
Motorola
Yes
64 words
Motorola
No
512 words
Intel
Motorola
0x0030
PHIF16
ERAMLO
&
ERAMHI
(128K)
ERAMLO
16-bit
16-bit
No
512 words
Intel
0x13
0x53
0x93
0x14
0x54
0x94
0x39
0x3B
0x3D
0x79
0x7B
0x7D
0xB9
0xBB
0xBD
0xF9
0xFB
0xFD
0x04
0x0030
Motorola
active-high
active-low
active-low
active-high
active-low
active-low
active-low
active-high
active-low
active-low
active-high
active-low
active-low
active-high
active-low
active-low
active-high
active-low
Intel
Motorola
0x0030
ERAMHI
Intel
Motorola
0x0111
IO
Intel
Motorola
0x0222
Intel
Motorola
0x0444
Intel
Motorola
0x0FFF
Intel
—
Test internal 1K IORAM0 memory segment—write result word to
ar3
(0x0FAB for passed and 0x0BAD for
failed).
Test internal 1K IORAM1 memory segment—write result word to
ar3
(0x0FAB for passed and 0x0BAD for
failed).
Test internal 60K DPRAM memory segment—write result word to
ar3
(0x0FAB for passed and 0x0BAD for
failed).
0x05
—
0x30
—
Command
Code
mwait
Setting
Function/Download
Download
From
Download
To
Configuration
PHIF16
Mode
MIOU0
DMA
Block
External
Bus
Logical
Transfer
PODS/
PDS
Byte-
Swapping
The boot routine configures the PHIF16 by writing to the
PHIFC
register. Specifically, the external bus configuration, logical transfer size, and
byte swapping are controlled by the PMODE and PCFIG fields, the mode is controlled by the PSTROBE field, and the PODS/PDS active-
low/high configuration is controlled by the PSTRB field. After the download is complete, the boot routine returns the PHIF16 to its initial state
(configures it for Intelmode with an 8-bit external bus and 8-bit logical transfers).
This is the size of each input DMA transfer that the boot routine directs the MIOU0 to perform without core intervention. MIOU0 performs
input DMA from the PHIF16 block. The boot routine configures the input block size by programming the
ILEN0
register.
§ The first 60 Kword locations of the segment are copied into the DPRAM.
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