參數(shù)資料
型號(hào)： DS80C411-FNY+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 97/102頁(yè)
文件大?。?/td> 0K
描述： IC MCU 75MHZ 16MB HP 100-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 90
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 75MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，SIO，UART/USART
外圍設(shè)備： 電源故障復(fù)位，WDT
輸入/輸出數(shù)： 64
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： ROM
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
94 of 102
Timers
The microcontroller provides four general-purpose timer/counters. Timers 0, 1, and 3 have three common modes of
operation. Each of the three can be used as a 13-bit timer/counter, 16-bit timer/counter, or 8-bit timer/counter with
auto-reload. Timer 0 can also operate as two 8-bit timer/counters. When operated as a counter, timers 0, 1, and 3
count pulses on the corresponding T0, T1, and T3 external pins. Timer 2 is a true 16-bit timer/counter with several
additional operating modes. With a 16-bit reload register, timer 2 supports other features such as 16-bit auto-
reload, capture, up/down count, and output clock generation. All four timer/counters default to the standard
oscillator frequency divided by 12 input clock but can be configured to run from the system clock divided by 4.
Timers 1 and 2 can also be configured to operate with an input clock equal to the system clock divided by 13.
Table 24 shows the SFRs and bits associated with the four timer/counters.
Table 24. Timer/Counter SFRs
TIMER/COUNTER FUNCTION
TIMER/
COUNTER 0
TIMER/
COUNTER 1
TIMER/
COUNTER 2
TIMER/
COUNTER 3
Timer/Counter Mode Selection and
Control
TMOD, TCON
T2MOD, T2CON
T3CM
Count Registers
TH0, TL0
TH1, TL1
TH2, TL2
TH3, TL3
8-Bit Reload Register
TH0
TH1
—
TH3
16-Bit Reload/Capture Registers
—
RCAP2H, RCAP2L
—
Timer Input Clock-Select Bit
CKCON.3
CKCON.4
CKCON.5
T3CM.5
Divide-by-13 Clock-Option Bit
—
T2MOD.4
T2MOD.3
—
Watchdog Timer
The watchdog is a free-running, programmable timer that can set a flag, cause an interrupt, and/or reset the
microcontroller if allowed to reach a preselected timeout. It can be restarted by software.
A typical application uses the watchdog timer as a reset source to prevent software from losing control. The
watchdog timer is initialized, selecting the timeout period and enabling the reset and/or interrupt functions. After
enabling the reset function, software must then restart the timer before its expiration or hardware resets the CPU.
In this way, if the code execution goes awry and software does not reset the watchdog as scheduled, the
microcontroller is put in reset, a known good state.
Software can select one of four timeout values as controlled by the WD1 and WD0 bits. Timeout values are precise
since they are a function of the crystal frequency. When the watchdog times out, the watchdog interrupt flag (WDIF
= WDCON.3) is set. If the watchdog interrupt source has been enabled, program execution immediately vectors to
the watchdog timer interrupt-service routine (code address = 63h). To enable the watchdog interrupt source, both
the EWDI (EIE.4) and EA (IE.7) bits must be set. Furthermore, setting the EWT (WDCON.1) bit allows the
watchdog timer to generate a reset exactly 512 system clocks following a timeout. To prevent the watchdog reset
from occurring in such a situation, the watchdog timer count must be reset (RWT = 1) or the watchdog-reset
function itself must be disabled (EWT = 0). Both the enable watchdog timer (EWT) reset and the reset watchdog
timer (RWT) control bits are protected by timed-access circuitry. This prevents errant software from accidentally
clearing or disabling the watchdog. When a watchdog timer reset condition occurs, the watchdog timer reset flag
(WTRF = WDCON.2) is set by the hardware. This flag can then be interrogated following a reset to determine
whether the reset was caused by the watchdog timer.
The watchdog interrupt is useful for systems that do not require a reset circuit. It sets the WDIF (watchdog
interrupt) flag 512 system clocks before setting the reset flag. Software can optionally enable this interrupt source,
which is independent of the watchdog-reset function. The interrupt is commonly used during the debug process to
determine where watchdog reset commands must be located in the application software. The interrupt also can
serve as a convenient time-base generator or can wake up the microcontroller from power-saving modes.
The watchdog timer is controlled by the clock control (CKCON) and the watchdog control (WDCON) SFRs.
CKCON.7 and CKCON.6 are WD1 and WD0 respectively, and they select the watchdog timeout period. Of course,
the 4X/2X (PMR.3) and CD1:0 (PMR.7:6) system clock control bits also affect the timeout period. Table 25 shows
the selection of timeout.
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DS80C411-FNY+ 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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