參數(shù)資料
型號: DS80C411-FNY+
廠商: Maxim Integrated Products
文件頁數(shù): 43/102頁
文件大?。?/td> 0K
描述: IC MCU 75MHZ 16MB HP 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 75MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),SIO,UART/USART
外圍設(shè)備: 電源故障復(fù)位,WDT
輸入/輸出數(shù): 64
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: ROM
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
45 of 102
Table 3. Extended Address Generation
P4CNT.5–3
P6.5
P6.4
P4.7
P4.6
P4.5
P4.4
MAX MEMORY ACCESSIBLE
per CE
000
I/O
32kB (Note 1)
001
I/O
A16
128kB
010
I/O
A17
A16
256kB
011
I/O
A18
A17
A16
512kB
100
I/O
A19
A18
A17
A16
1MB
101
I/O
A20
A19
A18
A17
A16
2MB (Note 4)
110 or 111(default)
A21
A20
A19
A18
A17
A16
4MB (Note 2)
Table 4. Chip-Enable Generation
P6CNT.2–0
PORT 6 PIN FUNCTION
P4CNT.2–0
PORT 4 PIN FUNCTION
P6.3
P6.2
P6.1
P6.0
P4.3
P4.2
P4.1
P4.0
000 (Note 3)
I/O
000
I/O
100
I/O
CE4
100
I/O
CE0
101
I/O
CE5
CE4
101
I/O
CE1
CE0
110
I/O
CE6
CE5
CE4
110
I/O
CE2
CE1
CE0
111 (Note 4)
CE7
CE6
CE5
CE4
111(default)
CE3
CE2
CE1
CE0
Note 1: Only 32kB of memory is accessible per chip enable for the P4CNT.5-3 = 000b setting, which means at least two chip enables are
needed in order to address the standard 16-bit (0–FFFFh) address range.
Note 2: The default P4CNT.5-3 = 111b setting (4MB accessible per CE) requires only four chip enables in order to access the maximum 24-bit
(0–FFFFFFh) address range.
Note 3: Default condition when the internal ROM is disabled.
Note 4: When the internal ROM is enabled, the default memory map is reconfigured to 2MB per CE, P4CNT.5-3 = 101b, and CE4 to CE7 are
enabled, P6CNT.2-0 = 111b.
External Data Memory Addressing
Using a similar implementation as was used to expand program memory access, the DS80C410 allows up to 4MB
of data memory access through four peripheral chip enables (PCE). The Port 5 control register (P5CNT; A2h) and
Port 6 control register (P6CNT; B2h) designate the number of peripheral chip enables and the maximum amount of
addressable data memory per peripheral chip enable. Table 5 shows which port pins are converted to peripheral
chip enables, along with the maximum memory accessible through each peripheral chip enable for P5CNT, P6CNT
bit settings.
Table 5. Peripheral Chip-Enable Generation
P5CNT.2–0
P5.7
P5.6
P5.5
P5.4
P6CNT.5–3
MAX MEMORY ACSESSIBLE per PCE
000 (default)
I/O
000 (default)
32kB
100
I/O
PCE0
001
128kB
101
I/O
PCE1
PCE0
010
256kB
110
I/O
PCE2
PCE1
PCE0
011
512kB
111
PCE3
PCE2
PCE1
PCE0
100
1MB
Demultiplexed External Memory Addressing
On power-up or following any reset, the DS80C410 defaults to the traditional 8051 external memory interface, with
the address MSB presented on Port 2 and the address LSB and data multiplexed on Port 0. The multiplexed mode
requires an external latch to demultiplex the address LSB and data. The DS80C410 provides an external pin (MUX)
that, when pulled high during a power-on reset, demultiplexes the address LSB and data. If demultiplexed mode is
enabled, the address LSB is provided on Port 7 and the data on Port 0. At the expense of consuming Port 7,
demultiplexed mode eliminates the external demultiplexing latch and the delay element associated with the latch. In
some cases, the removal of this timing delay allows use of slower, less expensive external memory devices.
Table 6 shows pin assignments for the multiplexed (traditional 8051) and demultiplexed external addressing
modes.
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