參數(shù)資料
型號: DS80C411-FNY+
廠商: Maxim Integrated Products
文件頁數(shù): 31/102頁
文件大小: 0K
描述: IC MCU 75MHZ 16MB HP 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 75MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),SIO,UART/USART
外圍設(shè)備: 電源故障復(fù)位,WDT
輸入/輸出數(shù): 64
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: ROM
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
34 of 102
PIN
NAME
FUNCTION
19
MDIO
MII Management Input/Output. The MII management I/O is the data pin for serial communication with the
external Ethernet PHY controller. In a read cycle, data is driven by the PHY to the MAC synchronously with
respect to the MDC clock. In a write cycle, data from the MAC is output to the external PHY synchronously with
respect to the MDC clock.
99
OW
1-Wire Data, I/O. The 1-Wire data pin is an open-drain, bidirectional data bus for the 1-Wire Bus Master.
External 1-Wire slave devices are connected to this pin. This pin must be pulled high by an external resistor,
normally 2.2k.
100
OWSTP
Strong Pullup Enable, Output. This 1-Wire pin is an open-drain active-low output used to enable an external
strong pullup for the 1-Wire bus. This pin must be pulled high by an external resistor, normally 10k. This
functionality helps recovery times when the 1-Wire bus is operated in overdrive and long-line standard
communication modes. It can optionally be enabled while the bus master is in the idle state for slave devices
requiring sustained high-current operation.
FEATURES (continued)
Full-Function CAN 2.0B Controller
15 Message Centers
Supports Standard (11-Bit) and Extended (29-Bit)
Identifiers and Global Masks
Media Byte Filtering to Support DeviceNet, SDS,
and Higher Layer CAN Protocols
Auto-Baud Mode and SIESTA Low-Power Mode
Integrated Primary System Logic
16 Total Interrupt Sources with Six External
Four 16-Bit Timer/Counters
2x/4x Clock Multiplier Reduces Electromagnetic
Interference (EMI)
Programmable Watchdog Timer
Oscillator-Fail Detection
Programmable IrDA Clock
Advanced Power Management
Energy Saving 1.8V Core
3.3V I/O Operation, 5V Tolerant
Power-Management, Idle, and Stop Mode
Operations with Switchback Feature
Ethernet and CAN Shutdown Control for Power
Conservation
Early Warning Power-Fail Interrupt
Power-Fail Reset
Enhanced Memory Architecture
Selectable 8/10-Bit Stack Pointer for High-Level
Language Support
64kBytes Additional On-Chip SRAM Usable as
Program/Data Memory
16-Bit/24-Bit Paged/24-Bit Contiguous Modes
Selectable Multiplexed/Nonmultiplexed External
Memory Interface
Merged Program/Data Memory Space Allows In-
System Programming
Defaults to True 8051-Memory Compatibility
DeviceNet is a trademark of Open DeviceNet Vendor Association, Inc.
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