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| 型號： | DS80C411-FNY+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 95/102頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 75MHZ 16MB HP 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | 80C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 75MHz |
| 連通性： | 1 線，CAN，EBI/EMI，以太網(wǎng)，SIO，UART/USART |
| 外圍設(shè)備： | 電源故障復(fù)位，WDT |
| 輸入/輸出數(shù)： | 64 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | ROM |
| RAM 容量： | 64K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.62 V ~ 3.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 托盤 |
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DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
92 of 102
EN_FOW (Bit 2): Enable Force OW. Setting the EN_FOW bit to a logic 1 allows the bus master to force the OW
line low using FOW (bit 2 of the command register). Clearing the EN_FOW bit to a logic 0 disables the use of the
FOW bit.
STPEN (Bit 3): Strong Pullup Enable. Setting the STPEN bit to a logic 1 enables functionality for the OWSTP
output pin. The OWSTP pin serves as the enable signal to an external strong pullup device. This functionality is
used for meeting the recovery time requirement in overdrive mode and long-line standard communication. When
enabled (STPEN = 1), OWSTP goes active-low any time the master is not pulling the OW line low or waiting to read
data from a slave during a communication sequence. Once the communication sequence is complete, the OWSTP
output is released. Note that when the master is in the idle state, the STP_SPLY bit must also be set to logic 1 (in
addition to STPEN = 1) in order for the OWSTP pin to remain in the active-low state. Clearing the STPEN bit to
logic 0 disables all OWSTP pin functionality.
STP_SPLY (Bit 4): Strong Pullup Supply Mode. When the OWSTP pin is enabled (STPEN = 1), setting the
STP_SPLY bit to logic 1 results in an active-low output for the OWSTP pin being sustained when the master is in an
idle state. Thus, when the OWSTP signal gates an external P-channel pullup, STP_SPLY = 1 can be used to
enable a stiff supply voltage to slave devices requiring high current during operation. Clearing the bit to logic 0
disables the strong pullup on the OWSTP pin when the master is idle. This bit has no affect when the OWSTP pin is
disabled (STPEN = 0).
BIT_CTL (Bit 5): Bit-Banging Mode. Setting this bit to logic 1 place the master into the bit-banging mode of
operation. In the bit-banging mode, only the least significant bit of the transmit/receive register is sent or received
before the associated interrupt flag occurs (signaling the end of the transaction). Clearing the bit leaves the bus
master operating in full-byte boundaries.
OD (Bit 6): Overdrive Mode. Setting this bit to a logic 1 places the master into overdrive mode, effectively
changing the bus master timing to match the 1-Wire timing for overdrive mode as outlined in The Book of iButton
Standards. Clearing the OD bit to a logic 0 leaves the master operating with standard mode timing.
EOWMI (Bit 7): Enable 1-Wire Master Interrupt. Setting this bit to a logic 1 enables the 1-Wire master interrupt
request to the CPU for any of the 1-Wire interrupt sources that have been individually enabled in the interrupt
enable register (xxxxx011b). Since the 1-Wire master interrupt and external interrupt 5 share the same interrupt
flag (IE5; EXIF.7), both cannot be used simultaneously. Thus, enabling the 1-Wire interrupt source effectively
disables the external interrupt 5 source.
1-Wire Interrupts
The 1-Wire bus master can be configured to generate an interrupt request to the CPU on the occurrence of a
number of 1-Wire-related events or conditions. These include the following: presence-detect, transmit buffer empty,
transmit shift-register empty, receive buffer full, receive shift-register full, 1-Wire short, and 1-Wire low. Each of
these potential 1-Wire interrupt sources has a corresponding enable bit and flag bit. Each flag bit in the interrupt
flag register (xxxxx010b) is set, independent of the interrupt enable bit, when the associated event or condition
occurs. In order for the interrupt flag to generate an interrupt request to the CPU, however, the individual enable bit
for the source along with the 1-Wire bus master interrupt enable bit (EOWMI; control register bit 7), and global
interrupt enable bit (EA; IE.7) must both be set to a logic 1. To clear the 1-Wire bus master interrupt, a read of the
interrupt flag register must always be performed by software. Table 22 summarizes the 1-Wire bus master interrupt
sources.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| DS80C411-FNY+ | 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80CH11 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:System Energy Manager |
| DS80CH11+E02 | 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11+E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11+E02 System Energy Managers |
| DS80CH11-E02 | 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11-E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11-E02 System Energy Managers |
| DS80E100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
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