參數(shù)資料
型號: DS21Q50N
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 67/99頁
文件大?。?/td> 325K
代理商: DS21Q50N
DS21Q50
Page 67 of 99
19.1 RECEIVE CLOCK AND DATA RECOVERY
The DS21Q50 contains a digital clock recovery system. See Figure 4-1 and Figure
19-1
for more details. The
device couples to the receive E1 shielded twisted pair or COAX via a 1:1 transformer. See
Table
19-2
for transformer details. The 2.048 MHz clock attached at the MCLK pin is internally multiplied by 16
via an internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the
PLL circuit to form a 16 times over-sampler which is used to recover the clock and data. This over-sampling
technique offers outstanding jitter tolerance (see Figure 19-4).
Normally, RCLK is the recovered clock from the E1 AMI/HDB3 waveform presented at the RTIP and RRING
inputs. When no AMI signal is present at RTIP and RRING, a Receive Carrier Loss (RCL) condition will occur
and the RCLK will be sourced from the clock applied at the MCLK pin. If the jitter attenuator is either placed in
the transmit path or is disabled, RCLK can exhibit slightly shorter high cycles of the clock. This is due to the
highly over-sampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the
case in most applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. Please see
the Receive AC Timing Characteristics in Section 24.4 for more details.
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