參數(shù)資料
型號(hào)： DS21Q50N
英文描述： Telecommunication IC
中文描述： 通信集成電路
文件頁數(shù)： 39/99頁
文件大?。?/td> 325K
代理商： DS21Q50N
DS21Q50
Page 39 of 99
Register Name:
Register Description:
Register Address:
Bit #
SYM
RSA1
SYMBOL
RSA1
SR1
STATUS REGISTER 1
0A Hex
7
6
5
4
3
2
1
0
RDMA
RSA0
RSLIP
RUA1
RRA
RCL
RLOS
BIT NAME AND DESCRIPTION
7
Receive Signaling All Ones.
Set when the contents of timeslot 16
contains less than three zeros over 16 consecutive frames. This alarm is
not disabled in the CCS signaling mode. Both RSA1 and RSA0 will be
set if a change in signaling is detected.
6
Receive Distant MF Alarm.
Set when bit–6 of timeslot 16 in frame 0
has been set for two consecutive multiframes. This alarm is not disabled
in the CCS signaling mode.
5
Receive Signaling All Zeros.
Set when over a full MF, timeslot 16
contains all zeros. Both RSA1 and RSA0 will be set if a change in
signaling is detected.
4
Receive Elastic Store Slip.
Set when the elastic store has either
repeated or deleted a frame of data.
3
Receive Unframed All Ones.
Set when an unframed all ones code is
received at RPOSI and RNEGI.
2
Receive Remote Alarm.
Set when a remote alarm is received at
RPOSI and RNEGI.
1
Receive Carrier Loss.
Set when 255 (or 2048 if CCR2.1=1)
consecutive zeros have been detected at RTIP and RRING. (note: a
receiver carrier loss based on data received at RPOSI and RNEGI is
available in the HSR register)
0
Receive Loss of Sync.
Set when the device is not synchronized to the
receive E1 stream.
RDMA
RSA0
RSLIP
RUA1
RRA
RCL
RLOS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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