參數(shù)資料
型號(hào)： DS21Q50N
英文描述： Telecommunication IC
中文描述： 通信集成電路
文件頁數(shù)： 4/99頁
文件大?。?/td> 325K
代理商： DS21Q50N
DS21Q50
Page 4 of 99
1. LIST OF FIGURES
Figure 1-1 DS21Q50 QUAD TRANSCEIVER.............................................................................................8
Figure 3-1 SERIAL PORT OPERATION MODE 1...................................................................................21
Figure 3-2 SERIAL PORT OPERATION MODE 2...................................................................................22
Figure 3-3 SERIAL PORT OPERATION MODE 3...................................................................................23
Figure 3-4 SERIAL PORT OPERATION MODE 4...................................................................................23
Figure 16-1 EXTERNAL ANALOG CONNECTIONS (BASIC CONFIGURATION).............................69
Figure 16-2 EXTERNAL ANALOG CONNECTIONS (PROTECTED INTERFACE).............................70
Figure 16-3 TRANSMIT WAVEFORM TEMPLATE ...............................................................................71
Figure 16-4 JITTER TOLERANCE............................................................................................................73
Figure 16-5 JITTER ATTENUATION........................................................................................................73
Figure 17-1 CMI CODING........................................................................................................................75
Figure 17-2 EXAMPLE OF CMI CODE VIOLATION (CV)....................................................................75
Figure 18-1 IBO CONFIGURATION USING 2 DS21Q50 TRANSCEIVERS (8 E1 Lines)......................78
Figure 19-1 RECEIVE FRAME AND MULTIFRAME TIMING...............................................................79
Figure 19-2 RECEIVE BOUNDARY TIMING (with elastic store disabled)................................................79
Figure 19-3 RECEIVE BOUNDARY TIMING (with elastic store enabled).................................................79
Figure 19-4 RECEIVE INTERLEAVE BUS OPERATION........................................................................80
Figure 19-5 TRANSMIT FRAME AND MULTIFRAME TIMING............................................................81
Figure 19-6 TRANSMIT BOUNDARY TIMING.......................................................................................81
Figure 19-7 TRANSMIT INTERLEAVE BUS OPERATION....................................................................82
Figure 19-8 DS21Q50 FRAMER SYNCHRONIZATION FLOWCHART................................................83
Figure 19-9 DS21Q50 TRANSMIT DATA FLOW....................................................................................84
Figure 21-1 INTEL BUS READ AC TIMING (BTS=0 / MUX = 1)...........................................................87
Figure 21-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1)..................................................................87
Figure 21-3 MOTOROLA BUS AC TIMING (BTS = 1 / MUX = 1).........................................................88
Figure 21-4 INTEL BUS READ TIMING (BTS=0 / MUX=0)....................................................................90
Figure 21-5 INTEL BUS WRITE TIMING (BTS=0 / MUX=0)..................................................................90
Figure 21-6 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0)........................................................91
Figure 21-7 MOTOROLA BUS WRITE TIMING (BTS=1 / MUX=0).......................................................91
Figure 21-8 SERIAL BUS TIMING (BIS1 = 1, BIS0 = 0)..........................................................................92
Figure 21-9 RECEIVE AC TIMING (Receive elastic store disabled)...........................................................94
Figure 21-10 RECEIVE AC TIMING (Receive elastic store enabled)..........................................................95
Figure 21-11 TRANSMIT AC TIMING (IBO Disabled).............................................................................97
Figure 21-12 TRANSMIT AC TIMING (IBO Enabled)..............................................................................97
Figure 21-13 NRZ INPUT AC TIMING.....................................................................................................98
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DS21Q552 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V Quad T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q552+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V Quad T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q552B 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
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