參數(shù)資料
型號(hào)： DS21Q50N
英文描述： Telecommunication IC
中文描述： 通信集成電路
文件頁(yè)數(shù)： 15/99頁(yè)
文件大?。?/td> 325K
代理商： DS21Q50N
DS21Q50
Page 15 of 99
PIN FUNCTION DESCRIPTION
5.1.1 SYSTEM (BACKPLANE) INTERFACE PINS
Signal Name:
TCLK
Signal Description:
Transmit Clock
Signal Type:
Input
A 2.048 MHz primary clock. Used to clock data through the transmit formatter.
Signal Name:
TSER
Signal Description:
Transmit Serial Data
Signal Type:
Input
Transmit NRZ serial data. Sampled on the falling edge of TCLK when IBO disabled. Sampled on the falling
edge of SYSCLK when the IBO function is enabled.
Signal Name:
TSYNC
Signal Description:
Transmit Sync
Signal Type:
Input / Output
As an input, pulse at this pin will establish either frame or multiframe boundaries for the transmitter. As an output,
can be programmed to output either a frame or multiframe pulse.
Signal Name:
RSER
Signal Description:
Receive Serial Data
Signal Type:
Output
Received NRZ serial data. Updated on rising edges of RCLK when the receive elastic store is disabled. Updated
on the rising edges of SYSCLK when the receive elastic store is enabled.
Signal Name:
RSYNC
Signal Description:
Receive Sync
Signal Type:
Input/Output
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame or CAS/CRC4 multiframe
boundaries. If the receive elastic store is enabled, then this pin can be enabled to be an input at which a frame
boundary pulse synchronous with SYSCLK is applied.
Signal Name:
SYSCLK
Signal Description:
System Clock
Signal Type:
Input
2.048MHz clock that is used to clock data out of the receive elastic store. When the Interleave Bus Option is
enable this can be a 4.096MHz, 8.192MHz or 16.384MHz clock
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相關(guān)代理商/技術(shù)參數(shù)
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