參數(shù)資料
型號(hào)： DS21Q50N
英文描述： Telecommunication IC
中文描述： 通信集成電路
文件頁(yè)數(shù)： 28/99頁(yè)
文件大?。?/td> 325K
代理商： DS21Q50N
DS21Q50
Page 28 of 99
Register Name:
Register Description:
Register Address:
Bit #
SYM
SYMBOL
IFSS
TCR
TRANSMIT CONTROL REGISTER
11 Hex
7
6
5
4
3
2
1
0
IFSS
TFPT
AEBE
TUA1
TSiS
TSA1
TSM
TSIO
BIT NAME AND DESCRIPTION
7
Internal Frame Sync Select.
0 = TSYSC normal
1 = If TSYNC is in the INPUT mode (TSIO = 0) then TSYNC is
internally replaced by the recovered receive frame sync. The TSYNC
pin is ignored
1 = If TSYNC is in the OUTPUT mode (TSIO = 1) then TSYNC
outputs the recovered multiframe frame sync.
6
0 = FAS bits/Sa bits/Remote Alarm sourced internally from the TAF
and TNAF registers
1 = FAS bits/Sa bits/Remote Alarm sourced from TSER
5
Automatic E–Bit Enable.
0 = E–bits not automatically set in the transmit direction
1 = E–bits automatically set in the transmit direction
4
Transmit Unframed All Ones.
0 = transmit data normally
1 = transmit an unframed all one’s code
3
Transmit International Bit Select.
0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (in this mode, TCR.6
must be set to 0)
2
Transmit Signaling All Ones.
0 = normal operation
1 = force timeslot 16 in every frame to all ones
1
TSYNC Mode Select.
0 = frame mode (see the timing in Section 22.2)
1 = CAS and CRC4 multiframe mode (see the timing in Section 22.2)
0
TSYNC I/O Select.
0 = TSYNC is an input
1 = TSYNC is an output
TFPT
Transmit Timeslot 0 Pass Through.
AEBE
TUA1
TSiS
TSA1
TSM
TSIO
NOTE: See Figure 22-9 for more details about how the Transmit Control Register affects the operation of the
DS21Q50.
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