參數(shù)資料
型號: DS21Q50N
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 41/99頁
文件大?。?/td> 325K
代理商: DS21Q50N
DS21Q50
Page 41 of 99
Register Name:
Register Description:
Register Address:
Bit #
SYM
SYMBOL
RMF
SR2
STATUS REGISTER 2
0B Hex
7
6
5
4
3
2
1
0
RMF
RAF
TMF
SEC
TAF
LOTC
RCMF
PRBSD
BIT NAME AND DESCRIPTION
7
Receive CAS Multiframe
. Set every 2 ms (regardless if CAS
signaling is enabled or not) on receive multiframe boundaries.
6
Receive Align Frame.
Set every 250 ms at the beginning of align
frames. Used to alert the host that Si and Sa bits are available in the
RAF and RNAF registers.
5
Transmit Multiframe.
Set every 2 ms (regardless if CRC4 is enabled)
on transmit multiframe boundaries.
4
One Second Timer.
Set on increments of one second based on RCLK.
If CCR2.7=1, then this bit will be set every 62.5 ms instead of once a
second.
3
Transmit Align Frame.
Set every 250 s at the beginning of align
frames. Used to alert the host that the TAF and TNAF registers need to
be updated.
2
Loss of Transmit Clock.
Set when the TCLK pin has not transitioned
for one channel time (or 3.9 ms). Will force the LOTC pin high if
enabled via TCR2.0.
1
Receive CRC4 Multiframe.
Set on CRC4 multiframe boundaries; will
continue to be set every 2 ms on an arbitrary boundary if CRC4 is
disabled.
0
Pseudo Random Bit Sequence Detect.
When receive PRBS is
enabled this bit will be set when the 2
15
-1 PRBS pattern is detected at
RPOS and RNEG. The PRBS pattern can be framed, un-framed, or in
a specific time slot.
RAF
TMF
SEC
TAF
LOTC
RCMF
PRBSD
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