參數(shù)資料
型號(hào)： DS21Q50N
英文描述： Telecommunication IC
中文描述： 通信集成電路
文件頁數(shù)： 63/99頁
文件大小： 325K
代理商： DS21Q50N
DS21Q50
Page 63 of 99
18. USER CONFIGURABLE OUTPUTS
There are two user configurable output pins for each transceiver, OUTA and OUTB. These pins can be
programmed to output various clocks, alarms for line monitoring, logic 0 and 1 levels to control external circuitry
or access transmit data between the framer and transmit line interface unit. OUTA and OUTB can be active low
or active high when operating as clock and alarm outputs. OUTA is active high if OUTAC.4 =1, and active low
if OUTAC.3 = 0. OUTB is active high if OUTBC.4 =1, and active low if OUTBC.4 = 0. See Table 18-1. For
controlling external circuitry, mode 0000 is selected. In this configuration, the OUTA pin will follow OUTAC.4
and the OUTB pin will follow OUTBC.4.
The OUTAC register also contains a control bit for CMI operation. Please see section 19 for details on CMI
operation.
Register Name:
OUTAC
Register Description:
OUTA CONTROL REGISTER
Register Address:
1A Hex
Bit #
7
6
5
4
SYM
TTLIE
CMII
CMIE
OA4
OA3
SYMBOL
BIT
TTLIE
7
TTL Input Enable.
When this bit is set, the receiver can accept TTL
positive and negative data at the RTIP and RRING inputs. The data is
clocked in on the falling edge of MCLK.
CMII
6
CMI Invert.
See section 20 for details.
0 = CMI input data not inverted
1 = CMI input data inverted
CMIE
5
CMI Enable.
See section 20 for details.
0 = CMI disabled
1 = CMI enabled
OA4
4
OUTA control bit 4.
Inverts OUTA output
OA3
3
OUTA control bit 3.
See Table 18-1 for details.
OA2
2
OUTA control bit 2.
See Table 18-1 for details.
OA1
1
OUTA control bit 1.
See Table 18-1 for details.
OA0
0
OUTA control bit 0.
See Table 18-1 for details.
3
2
1
0
OA2
OA1
OA0
NAME AND DESCRIPTION
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