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參數(shù)資料
| 型號： | DS21Q50N |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 25/99頁 |
| 文件大?。?/td> | 325K |
| 代理商： | DS21Q50N |
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DS21Q50
Page 25 of 99
NOTES:
1. Test Registers are used only by the factory; these registers must be cleared (set to all zeros) on power– up
initialization to insure proper operation.
2 The Device ID register and the System Clock Interface Control register exist in Transceiver #1 only.
(TS0, TS1 = 0)
7. CONTROL, ID, AND TEST REGISTERS
The operation of the DS21Q50 is configured via a set of seven control registers. Typically, the control registers
are only accessed when the system is first powered up. Once the device has been initialized, the control registers
will only need to be accessed when there is a change in the system configuration. There is one Receive Control
Register (RCR), one Transmit Control Registers (TCR), and five Common Control Registers (CCR1 to CCR5).
Each of these registers are described in this section.
There is a device Identification Register (IDR) at address 0Fh. The MSB of this read–only register is fixed to a
one indicating that an E1 Quad Transceiver is present. The next 3 MSBs are reserved for future use. The lower
4 bits of the device ID register are used to identify the revision of the device. This register exists in Transceiver
#1 only. (TS0, TS1 = 0)
The Test registers at addresses 1E, 1F, and 2F hex are used by the factory in testing the DS21Q50. On power-
up, the Test registers should be set to 00h in order for the DS21Q50 to operate properly.
Register Name:
IDR
Register Description:
DEVICE IDENTIFICATION REGISTER
Register Address:
0F Hex
Bit #
7
6
5
4
SYM
1
0
0
0
ID3
SYMBOL
BIT
1
7
Bit 7.
0
6
Bit 6.
0
5
Bit 5.
0
4
Bit 4.
ID3
3
Chip Revision Bit 3.
MSB of a decimal code that represents the chip
revision.
ID2
1
Chip Revision Bit 2.
ID1
2
Chip Revision Bit 1.
ID0
0
Chip Revision Bit 0.
LSB of a decimal code that represents the chip
revision.
3
2
1
0
ID2
ID1
ID0
NAME AND DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21Q55DK | Quad T1/E1/J1 Transceiver Design Kit Daughter Card |
| DS21Q55 | Quad T1/E1/J1 Transceiver |
| DS21Q55N | Quad T1/E1/J1 Transceiver |
| DS21S07A | SCSI Terminator |
| DS21S07AE | Terminator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q55 | 功能描述:IC TXRX QUAD T1/E1/J1 SCT 256BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| DS21Q552 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V Quad T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q552+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V Quad T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q552B | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS21Q552BN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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