參數(shù)資料
型號(hào): DS21Q50N
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁(yè)數(shù): 37/99頁(yè)
文件大?。?/td> 325K
代理商: DS21Q50N
DS21Q50
Page 37 of 99
Register Name:
Register Description:
Register Address:
Bit #
SYM
CSC5
SYMBOL
CSC5
SSR
SYNCHRONIZER STATUS REGISTER
09 Hex
7
6
5
4
3
2
1
0
CSC4
CSC3
CSC2
CSC0
FASSA CASSA
CRC4SA
BIT NAME AND DESCRIPTION
7
CRC4 Sync Counter Bit 5.
MSB of the 6–bit counter.
6
CRC4 Sync Counter Bit 4.
5
CRC4 Sync Counter Bit 3.
4
CRC4 Sync Counter Bit 2.
3
CRC4 Sync Counter Bit 0.
LSB of the 6–bit counter. Counter Bit 1 is
not accessible.
2
FAS Sync Active.
Set while the synchronizer is searching for alignment
at the FAS level.
1
CAS MF Sync Active.
Set while the synchronizer is searching for the
CAS MF alignment word.
0
CRC4 MF Sync Active.
Set while the synchronizer is searching for the
CRC4 MF alignment word.
CSC4
CSC3
CSC2
CSC0
FASSA
CASSA
CRC4SA
8.1 CRC4 SYNC COUNTER
The CRC4 Sync Counter increments each time the 8 ms CRC4 multiframe search times out. The counter is
cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be
cleared by disabling the CRC4 mode (CCR1.0=0). This counter is useful for determining the amount of time the
framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at
the CRC4 level cannot be obtained within 400 ms, then the search should be abandoned and proper action
taken. The CRC4 Sync Counter will rollover.
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