參數(shù)資料
型號(hào)： COM20019ILJP
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
中文描述： 1 CHANNEL(S), 312.5K bps, LOCAL AREA NETWORK CONTROLLER, PQCC28
封裝： PLASTIC, LCC-28
文件頁(yè)數(shù)： 59/65頁(yè)
文件大小： 386K
代理商： COM20019ILJP
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 09-25-07
Page 62
SMSC COM20019I
DATASHEET
Chapter 10 APPENDIX A
This appendix describes the function of the NOSYNC and EF bits.
10.1
NOSYNC Bit
The NOSYNC bit controls whether or not the RAM initialization sequence requires the line to be idle by
enabling or disabling the SYNC command during initialization. It is defined as follows:
NOSYNC: Enable/Disable SYNC command during initialization. NOSYNC=0, Enable (Default): the line
has to be idle for the RAM initialization sequence to be written, NOSYNC=1, Disable: the line does not
have to be idle for the RAM initialization sequence to be written.
The following discussion describes the function of this bit:
During initialization, after the CPU writes the Node ID, the COM20019I will write "D1"h data to Address
000h and Node-ID to Address 001h of its internal RAM within 96uS. These values are read as part of the
diagnostic test. If the D1 and Node-ID initialization sequence cannot be read, the initialization routine will
report it as a device diagnostic failure. These writes are controlled by a micro-program which sometimes
waits if the line is active; SYNC is the micro-program command that causes the wait. When the micro-
program waits, the initial RAM write does not occur, which causes the diagnostic error. Thus in this case,
if the line is not idle, the initialization sequence may not be written, which will be reported as a device
diagnostic failure.
However, the initialization sequence and diagnostics of the COM20019I should be independent of the
network status. This is accomplished through some additional logic to decode the program counter,
enabled by the NOSYNC bit. When it finds that the micro-program is in the initialization routine, it disables
the SYNC command. In this case, the initialization will not be held up by the line status.
Thus, by setting the NOSYNC bit, the line does not have to be idle for the RAM initialization sequence to
be written.
10.2
EF Bit
The EF bit controls several modifications to internal operation timing and logic. It is defined as follows:
EF: Enable/Disable the new internal operation timing and logic refinements. EF=0: (Default) Disable the
new internal operation timing (the timing is the same as in the COM20020 Rev. B); EF=1: Enable the new
internal operation timing.
The EF bit controls the following timing/logic refinements in the COM20019I:
A)
Extend Interrupt Disable Time
While the interrupt is active (nINTR pin=0), the interrupt is disabled by writing the Clear Tx/Rx interrupt and
Clear Flag command and by reading the Next-ID register. This minimum disable time is changed by the
Data Rate.
Setting the EF bit will change the minimum disable time to always be more than 200 nS.
This is done by
changing the clock which is supplied to the Interrupt Disable logic. The frequency of this clock is always
less than 20MHz .
B)
Synchronize the Pre-Scalar Output
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
COM20019I-LJP 制造商:SMSC 制造商全稱:SMSC 功能描述:Low Cost ARCNET(ANSI 878.1) Controller with 2k X 8 On-Board RAM
COM20019ILJP3V 功能描述:網(wǎng)絡(luò)控制器與處理器 IC ARCNET Contrllr RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
COM20019ILJPTR 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Arcnet (ANSI 878.1) Controllr 2k x 8 Ram RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
COM20019IP 制造商:Rochester Electronics LLC 功能描述:- Bulk
COM20020 制造商:SMSC 制造商全稱:SMSC 功能描述:COM20020 3.3V ULANC Universal Local Area Network Controller with 2K x 8 On-Board RAM
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