參數(shù)資料
型號(hào): COM20019ILJP
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
中文描述: 1 CHANNEL(S), 312.5K bps, LOCAL AREA NETWORK CONTROLLER, PQCC28
封裝: PLASTIC, LCC-28
文件頁(yè)數(shù): 48/65頁(yè)
文件大小: 386K
代理商: COM20019ILJP
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 09-25-07
Page 52
SMSC COM20019I
DATASHEET
Figure 8.5 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE
A0-A2
VALID DATA
VALID
D0-D7
nCS
t6
t1
t7
t3
t5
t4
t2
nRD
nWR
t10
t8
t9
Note 3
Note 2
Parameter
min
max
units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
15
10
5**
0
nS
Address Setup to nRD Active
Address Hold from nRD Inactive
nCS Setup to nRD Active
nCS Hold from nRD Inactive
Cycle Time (nRD Low to Next Time Low)
nRD Low to Valid Data
nRD High to Data High Impedance
4TARB
*
0
60
20
40**
20
nS
CASE 1: RBUSTMG bit = 0
nRD Low Width
nRD High Width
nWR
to nRD Low
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
nCS may become active after control becomes active, but the access time (t6)
will now be 45nS measured from the leading edge of nCS.
**
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
Note 1:
Note 2:
Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 3:
Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
**
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