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| 型號： | COM20019ILJP |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 微控制器/微處理器 |
| 中文描述： | 1 CHANNEL(S), 312.5K bps, LOCAL AREA NETWORK CONTROLLER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 30/65頁 |
| 文件大?。?/td> | 386K |
| 代理商： | COM20019ILJP |
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Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 09-25-07
Page 36
SMSC COM20019I
DATASHEET
The microcontroller interfaces to the COM20019I via software by accessing the various registers. These
actions are described in the Internal Registers section. The software flow for accessing the data buffer is
based on the Sequential Access scheme. The basic sequence is as follows:
Disable Interrupts
Write to Pointer Register High (specifying Auto-Increment mode)
Write to Pointer Register Low (this loads the address)
Enable Interrupts
Read or Write the Data Register (repeat as many times as necessary to empty or fill the buffer)
The pointer may now be read to determine how many transfers were completed.
The software flow for controlling the Configuration, Node ID, Tentative ID, and Next ID registers is
generally limited to the initialization sequence and the maintenance of the network map.
Additionally, it is necessary to understand the details of how the other Internal Registers are used in the
transmit and receive sequences and to know how the internal RAM buffer is properly set up.
The
sequence of events that tie these actions together is discussed as follows.
6.4.1
Selecting RAM Page Size
During normal operation, the 2K x 8 of RAM is divided into four pages of 512 bytes each. The page to be
used is specified in the "Enable Transmit (Receive) from (to) Page fnn" command, where "nn" specifies
page 0, 1, 2, or 3. This allows the user to have constant control over the allocation of RAM.
When the Offset bit "f" (bit 5 of the "Enable Transmit (Receive) from (to) Page fnn" command word) is set
to logic "1", an offset of 256 bytes is added to the page specified. For example: to transmit from the second
half of page 0, the command "Enable Transmit from Page fnn" (fnn=100 in this case) is issued by writing
0010 0011 to the Command Register. This allows a finer resolution of the buffer pages without affecting
software compatibility. This scheme is useful for applications which frequently use packet sizes of 256
bytes or less, especially for microcontroller systems with limited memory capacity. The remaining portions
of the buffer pages which are not allocated for current transmit or receive packets may be used as
temporary storage for previous network data, packets to be sent later, or as extra memory for the system,
which may be indirectly accessed.
If the device is configured to handle both long and short packets (see "Define Configuration" command),
then receive pages should always be 512 bytes long because the user never knows what the length of the
receive packet will be. In this case, the transmit pages may be made 256 bytes long, leaving at least 512
bytes free at any given time. Even if the Command Chaining operation is being used,
512 bytes is still guaranteed to be free because Command Chaining only requires two pages for transmit
and two for receive (in this case, two 256 byte pages for transmit and two 512 byte pages for receive,
leaving 512 bytes free). Please note that it is the responsibility of software to reserve 512 bytes for each
receive page if the device is configured to handle long packets. The COM20019I does not check page
boundaries during reception. If the device is configured to handle only short packets, then both transmit
and receive pages may be allocated as 256 bytes long, freeing at least 1KByte at any given time.
Even if the Command Chaining operation is being used, 1KByte is still guaranteed to be free because
Command Chaining only requires two pages for transmit and two for receive (in this case, a total of four
256 byte pages, leaving 1K free).
The general rule which may be applied to determine where in RAM a page begins is as follows:
Address = (nn x 512) + (f x 256).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| COM20019I-LJP | 制造商:SMSC 制造商全稱:SMSC 功能描述:Low Cost ARCNET(ANSI 878.1) Controller with 2k X 8 On-Board RAM |
| COM20019ILJP3V | 功能描述:網(wǎng)絡控制器與處理器 IC ARCNET Contrllr RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| COM20019ILJPTR | 功能描述:網(wǎng)絡控制器與處理器 IC Arcnet (ANSI 878.1) Controllr 2k x 8 Ram RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| COM20019IP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| COM20020 | 制造商:SMSC 制造商全稱:SMSC 功能描述:COM20020 3.3V ULANC Universal Local Area Network Controller with 2K x 8 On-Board RAM |
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