參數資料
型號： COM20019ILJP
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
中文描述： 1 CHANNEL(S), 312.5K bps, LOCAL AREA NETWORK CONTROLLER, PQCC28
封裝： PLASTIC, LCC-28
文件頁數： 23/65頁
文件大小： 386K
代理商： COM20019ILJP
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20019I
Page 3
Rev. 09-25-07
DATASHEET
TABLE OF CONTENTS
Chapter 1
GENERAL DESCRIPTION..................................................................................................... 5
Chapter 2
PIN CONFIGURATIONS........................................................................................................ 6
Chapter 3
DESCRIPTION OF PIN FUNCTIONS.................................................................................... 8
Chapter 4
PROTOCOL DESCRIPTION ............................................................................................... 11
4.1
NETWORK PROTOCOL............................................................................................................................11
4.2
DATA RATES.............................................................................................................................................11
4.3
NETWORK RECONFIGURATION .............................................................................................................11
4.4
BROADCAST MESSAGES........................................................................................................................12
4.5
EXTENDED TIMEOUT FUNCTION ...........................................................................................................12
4.5.1
Response Time ...................................................................................................................................12
4.5.2
Idle Time .............................................................................................................................................12
4.5.3
Reconfiguration Time ..........................................................................................................................13
4.6
LINE PROTOCOL ......................................................................................................................................13
4.6.1
Invitations To Transmit........................................................................................................................13
4.6.2
Free Buffer Enquiries ..........................................................................................................................13
4.6.3
Data Packets.......................................................................................................................................13
4.6.4
Acknowledgements .............................................................................................................................14
4.6.5
Negative Acknowledgements ..............................................................................................................14
Chapter 5
SYSTEM DESCRIPTION ..................................................................................................... 15
5.1
MICROCONTROLLER INTERFACE..........................................................................................................15
5.1.1
High Speed CPU Bus Timing Support ................................................................................................18
5.2
TRANSMISSION MEDIA INTERFACE ......................................................................................................19
5.2.1
Backplane Configuration .....................................................................................................................19
5.2.2
Differential Driver Configuration ..........................................................................................................20
5.2.3
Programmable TXEN Polarity .............................................................................................................20
Chapter 6
FUNCTIONAL DESCRIPTION............................................................................................. 23
6.1
MICROSEQUENCER.................................................................................................................................23
6.2
INTERNAL REGISTERS............................................................................................................................24
6.2.1
Interrupt Mask Register (IMR) .............................................................................................................24
6.2.2
Data Register ......................................................................................................................................24
6.2.3
Tentative ID Register ..........................................................................................................................25
6.2.4
Node ID Register.................................................................................................................................25
6.2.5
Next ID Register..................................................................................................................................25
6.2.6
Status Register....................................................................................................................................25
6.2.7
Diagnostic Status Register ..................................................................................................................26
6.2.8
Command Register .............................................................................................................................26
6.2.9
Address Pointer Registers ..................................................................................................................26
6.2.10
Configuration Register .....................................................................................................................26
6.2.11
Sub-Address Register .....................................................................................................................26
6.2.12
Setup 1 Register..............................................................................................................................26
6.2.13
Setup 2 Register..............................................................................................................................27
6.3
INTERNAL RAM ........................................................................................................................................35
6.3.1
Sequential Access Memory.................................................................................................................35
6.3.2
Access Speed .....................................................................................................................................35
6.4
SOFTWARE INTERFACE..........................................................................................................................35
6.4.1
Selecting RAM Page Size ...................................................................................................................36
6.4.2
Transmit Sequence .............................................................................................................................37
6.4.3
Receive Sequence ..............................................................................................................................38
6.5
COMMAND CHAINING..............................................................................................................................39
6.5.1
Transmit Command Chaining .............................................................................................................40
6.5.2
Receive Command Chaining ..............................................................................................................40
6.6
RESET DETAILS .......................................................................................................................................41
6.6.1
Internal Reset Logic ............................................................................................................................41
6.7
INITIALIZATION SEQUENCE ....................................................................................................................41
6.7.1
Bus Determination...............................................................................................................................41
6.8
IMPROVED DIAGNOSTICS ......................................................................................................................42
6.8.1
Normal Results:...................................................................................................................................43
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相關代理商/技術參數
參數描述
COM20019I-LJP 制造商:SMSC 制造商全稱:SMSC 功能描述:Low Cost ARCNET(ANSI 878.1) Controller with 2k X 8 On-Board RAM
COM20019ILJP3V 功能描述:網絡控制器與處理器 IC ARCNET Contrllr RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
COM20019ILJPTR 功能描述:網絡控制器與處理器 IC Arcnet (ANSI 878.1) Controllr 2k x 8 Ram RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
COM20019IP 制造商:Rochester Electronics LLC 功能描述:- Bulk
COM20020 制造商:SMSC 制造商全稱:SMSC 功能描述:COM20020 3.3V ULANC Universal Local Area Network Controller with 2K x 8 On-Board RAM
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