參數(shù)資料
型號(hào): COM20019ILJP
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
中文描述: 1 CHANNEL(S), 312.5K bps, LOCAL AREA NETWORK CONTROLLER, PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 52/65頁
文件大小: 386K
代理商: COM20019ILJP
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 09-25-07
Page 56
SMSC COM20019I
DATASHEET
Figure 8.9 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE
Data Hold from nWR High
nWR Low Width
nWR High Width
nRD
to nWR Low
A0-A2
VALID DATA
VALID
D0-D7
nCS
t6
t1
t7
t3
t4
t2
Note 2
nWR
nRD
t10
t8
t9
t5
Note 3
t5**
t1
t3
t5
t6
t7
t8
t9
t10
Parameter
Address Setup to nWR Active
nCS Setup to WR Active
Valid Data Setup to nWR High
min
15
5
10
20
max
4TARB
*
30***
units
nS
t4
nCS Hold from nWR Inactive
0
nS
t2
Address Hold from nWR Inactive
10
nS
Cycle Time (nWR
to Next
)**
***:
nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
Note 1:
Note 2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nWR to the leading edge
of the next nWR.
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3:
Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
**
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