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參數(shù)資料
| 型號： | CLC5902VLA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 調諧器 |
| 英文描述： | Dual Digital Tuner/AGC |
| 中文描述： | 1-BAND, AUDIO TUNER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 783K |
| 代理商： | CLC5902VLA |
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Rev. 3.05 May 27, 1999
8
1999 National Semiconductor Corporation
A[7:0]
48,50,52:57
ADDRESS BUS.
Active high
These pins are used to address the control registers within the chip. Each of the control registers within the
chip are assigned a unique address in a flat address space. A control register can be written to or read from
by setting
A[7:0]
to the register’s address.
RD
59
READ ENABLE.
Active low
This pin enables the chip to output the contents of the selected register on the
D[7:0]
pins when
CE
is also
low.
WR
58
WRITE ENABLE.
Active low
This pin enables the chip to write the value on the
D[7:0]
pins into the selected register when
CE
is also
low. This pin can also function as
RD/WR
if
RD
is held low.
CE
60
CHIP ENABLE.
Active low
This control strobe enables the read or write operation. The contents of the register selected by
A[7:0]
will
be output on
D[7:0]
when
RD
is low and
CE
is low. If
WR
is low and
CE
is low, then the selected register
will be loaded with the contents of
D[7:0]
.
AGC_EN
44
AGC ENABLE.
Active low
When enabled this pin starts the AGC counter. The AGC will operate until the counter decrements to zero
then the AGC holds the last setting.
TDO
116
TEST DATA OUT.
Active high
TDI
117
TEST DATA IN.
Active high with pull-up
TMS
118
TEST MODE SELECT.
Active high with pull-up
TCK
119
TEST CLOCK.
Active high
TRST
121
RESET.
Active low with pull-up
Asynchronous reset for TAP controller. Tie low or to
MR
if JTAG is not used.
SCAN_EN
122
SCAN ENABLE.
Active low with pull-up
Enables access to internal scan registers. Tie high. Used for manufacturing test only!
VSS
3,19,29,37,47,51,
61,68,76,83,89,
98,103,110,120
Ground. Quantity 15.
VDD
11,21,39,49,64,
74,79,85,92,107,
115,128
Power. Quantity 12.
Signal
Pin
DESCRIPTION
Table 1
CLC5902 Pin Descriptions
Timing Diagrams
Figure 5
CLC5902 Master Reset Timing
CK
t
MRH
t
MRA
t
MRSU
t
MRIC
MR
RD
or
WR
A|BSTROBE
t
MRSR
相關PDF資料 |
PDF描述 |
|---|---|
| CLC5903 | Dual Digital Tuner / AGC |
| CLC5903SM | Dual Digital Tuner / AGC |
| CLC5903VLA | Dual Digital Tuner / AGC |
| CLC5955 | 11-bit, 55MSPS Broadband Monolithic A/D Converter |
| CLC5955MTDX | 11-bit, 55MSPS Broadband Monolithic A/D Converter |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CLC5903 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Digital Tuner / AGC |
| CLC5903CISM/NOPB | 功能描述:上下轉換器 RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903SM | 功能描述:上下轉換器 RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903SM/NOPB | 功能描述:上下轉換器 RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903VLA | 功能描述:上下轉換器 RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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