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參數(shù)資料
| 型號： | CLC5902VLA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | Dual Digital Tuner/AGC |
| 中文描述： | 1-BAND, AUDIO TUNER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大小： | 783K |
| 代理商： | CLC5902VLA |
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Rev. 3.05 May 27, 1999
12
1999 National Semiconductor Corporation
Detailed Description
Control Interface
The CLC5902 is configured by writing control informa-
tion into 148 control registers within the chip. The con-
tents of these control registers and how to use them are
described in Table 5. The registers are written to or read
from using the
D[7:0]
,
A[7:0]
,
CE
,
RD
and
WR
pins (see
Table 1 for pin descriptions). This interface is designed to
allow the CLC5902 to appear to an external processor as a
memory mapped peripheral. See Figure 14 for details.
The control interface is asynchronous with respect to the
system clock,
CK
. This allows the registers to be written
or read at any time. In some cases this might cause an
invalid operation since the interface is not internally syn-
chronized. In order to assure correct operation,
SI
must be
asserted after the control registers are written.
The
D[7:0]
,
A[7:0]
,
WR
,
RD
and
CE
pins should not be
driven above the positive supply voltage.
Master Reset
A master reset pin,
MR
, is provided to initialize the
CLC5902 to a known condition and should be strobed
after power up. This signal will clear all sample data and
all user programmed data (filter coefficients and AGC set-
tings). All outputs will be disabled (tri-stated).
ASTROBE
and
BSTROBE
will be asserted to initialize the DVGA
values. Table 5 describes the control register default val-
ues.
Synchronizing Multiple CLC5902 Chips
A system containing two or more CLC5902 chips will
need to be synchronized if coherent operation is desired.
To synchronize multiple CLC5902 chips, connect all of
the sync input pins together so they can be driven by a
common sync strobe. Synchronization occurs on the rising
edge of
CK
when
SI
goes back high. When
SI
is asserted
all sample data will be flushed immediately, the numeri-
cally controlled oscillator (NCO) phase offset will be ini-
tialized, the NCO dither generators will be reset, and the
CIC decimation ratio will be initialized. Only the configu-
ration data loaded into the microprocessor interface
remains unaffected.
SI
may be held low as long as desired after a minimum of
4
CK
periods.
Input Source
The input crossbar switch allows either
AIN
,
BIN
, or a
test register to be routed to the channel A or channel B
AGC/DDC. The AGC outputs,
AGAIN
and
BGAIN
, are
not switched. If
AIN
and
BIN
are exchanged the AGC
loop will be open and the AGCs will not function properly.
AIN
and
BIN
should meet the timing requirements shown
in Figure 7.
Selecting the test register as the input source allows the
AGC or DDC operation to be verified with a known input.
See the test and diagnostics section for further discussion.
Down Converters
A detailed block diagram of each DDC channel is shown
in Figure 15. Each down converter uses a complex NCO
and mixer to quadrature downconvert a signal to base-
band. The “FLOAT TO FIXED CONVERTER” treats the
15-bit mixer output as a mantissa and the AGC output,
EXP
, as a 3-bit exponent. It performs a bit shift on the data
based on the value of
EXP
. This bit shifting is used to
expand the compressed dynamic range resulting from the
DVGA operation. The DVGA gain is adjusted in 6dB
steps which are equivalent to each digital bit shift.
The exponent (
EXP
) can be forced to its maximum value
by setting the EXP_INH bit. If
the signal after the “FLOAT TO FIXED CONVERTER” is
is the DDC input,
EQ. 1
for the I component. Changing the ‘cos’ to ‘sin’ in this
equation will provide the Q component.
NCO
S
D
C
FREQ_A
PHASE_A
S
F
F
F
F
D
8
D
D
S
Data @ F
CK
= F
S
(F
SAMPLE
)
2
D
C
T
F
EXPONENT
EXP
E
14
3
22
22
21
21
EXP
TO
OUTPUT
CIRCUIT
G
17
17
S
S
21
21
S
15
15
Figure 15
CLC5902 Down Converter, Channel A (Channel B is identical)
SIN
COS
I
Q
(from AGC)
x
3
n
( )
x
in
n
( )
MUXA
Data @ F
CK
/N
Data @ F
CK
/N*2
Data @ F
/N*2*F2_DEC
= O
FS
(Output F
SAMPLE
)
N = DEC + 1
x
in
n
( )
x
3
n
( )
x
in
n
( )
ω
n
(
)
cos
2
EXP
=
相關PDF資料 |
PDF描述 |
|---|---|
| CLC5903 | Dual Digital Tuner / AGC |
| CLC5903SM | Dual Digital Tuner / AGC |
| CLC5903VLA | Dual Digital Tuner / AGC |
| CLC5955 | 11-bit, 55MSPS Broadband Monolithic A/D Converter |
| CLC5955MTDX | 11-bit, 55MSPS Broadband Monolithic A/D Converter |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CLC5903 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Digital Tuner / AGC |
| CLC5903CISM/NOPB | 功能描述:上下轉換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903SM | 功能描述:上下轉換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903SM/NOPB | 功能描述:上下轉換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903VLA | 功能描述:上下轉換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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