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參數(shù)資料
| 型號： | CLC5902VLA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | Dual Digital Tuner/AGC |
| 中文描述： | 1-BAND, AUDIO TUNER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大小： | 783K |
| 代理商： | CLC5902VLA |
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1999 National Semiconductor Corporation
17
Rev. 3.05 May 27, 1999
Overall Channel Gain
The overall gain of the chip is a function of the amount of
decimation (N), the settings of the “SHIFT UP” circuit
(SCALE), the GAIN setting, the sum of the F1 coeffi-
cients, and the sum of the F2 coefficients. The overall gain
is shown below in Equation 2.
EQ. 2
Where:
EQ. 3
and:
EQ. 4
It is assumed that the DDC output words are treated as
fractional 2’s complement words. The numerators of
and
cients of F1 and F2, respectively. For the STD and GSM
sets,
and
are nearly equal to unity. Observe that
G
F
1
G
F
2
equal the sums of the impulse response coeffi-
the
ation so that the entire gain of the DRCS is independent of
term in EQ. 2 is cancelled by the DVGA oper-
the DVGA setting when EXP_INH=0. The appearing in
EQ. 2 is the result of the 6dB conversion loss in the mixer.
For full-scale square wave inputs the should be set to 1
to prevent signal distortion.
Data Latency and Group Delay
The latency from a sync event to data output is approxi-
mately 8N
CK
periods for F2 decimation by 2 and 24N
CK
periods for F2 decimation by 4. Actual non-zero data
output can be further delayed depending on the F1 and F2
filter coefficients.
Group Delay is approximately 90N
CK
periods for F2
decimation by 2 or 4.
Figure 25
CIC, F1, & F2 STD Passband Flatness
0
50
100
Frequency (KHz)
150
200
250
0.1
0.08
0.06
0.04
0.02
0
0.02
0.04
0.06
0.08
0.1
Combined Frequency Response of CIC/F1/F2 Using STD Set
M
Figure 26
CIC, F1, & F2 GSM frequency response
0
500
1000
1500
2000
2500
3000
100
80
60
40
20
0
Combined Frequency Response of CIC/F1/F2 Using GSM Set
M
Frequency (KHz)
F
= 52MHz
Decimation = 192
O
FS
= 270.83kHz
Figure 27
CIC, F1, & F2 GSM Passband Flatness
0
20
40
Frequency (KHz)
60
80
100
2
1.5
1
0.5
0
0.5
1
Combined Frequency Response of CIC/F1/F2 Using GSM Set
M
G
DDC
1
2
DEC
2
SCALE
1
+
(
)
4
44
–
AGAIN
1
EXP
_
INH
–
(
)
–
[
]
2
GAIN
G
F
1
G
F
2
=
G
F
1
h
1
i
( )
---------------------
2
21
∑
=
G
F
2
h
2
i
( )
---------------------
2
63
∑
=
G
F
1
G
F
2
AGAIN
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CLC5903 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Digital Tuner / AGC |
| CLC5903CISM/NOPB | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903SM | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903SM/NOPB | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903VLA | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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